A 1-mW 12-Gb/s continuous-time adaptive passive equalizer in 90-nm CMOS. - Dong Hun Shin; Ji-Eun Jang; Frank O'Mahony; C. Patrick Yue (CICC, 2009)

High-bandwidth power-scalable 10-bit pipelined ADC using bandwidth-reconfigurable operational amplifier. - Ji-Eun Jang; Yung-Kuang Miao; Yung-Pin Lee (ISCAS, 2010)

A pipelined analog-to-digital converter using incomplete-settling-without-slewing technique. - Kuan-Yu Lin; Ji-Eun Jang; Ching-Hsuan Hsieh; Yung-Pin Lee (ISCAS, 2010)

Comparator-based switched-capacitor pipelined ADC with background offset calibration. - Ji-Eun Jang (ISCAS, 2011)

True event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver example. - Ji-Eun Jang; Myeong-Jae Park; Dongyun Lee; Jaeha Kim (CICC, 2012)

Event-driven simulation of Volterra series models in SystemVerilog. - Ji-Eun Jang; Si-Jung Yang; Jaeha Kim (CICC, 2013)

An event-driven simulation methodology for integrated switching power supplies in SystemVerilog. - Ji-Eun Jang; Myeong-Jae Park; Jaeha Kim (DAC, 2013)

PPV-based modeling and event-driven simulation of injection-locked oscillators in SystemVerilog. - Jaeha Kim; Si-Jung Yang; Ji-Eun Jang (CICC, 2014)

Digital Analog Design: Enabling Mixed-Signal System Validation. - ByongChan Lim; Ji-Eun Jang; James Mao; Jaeha Kim; Mark Horowitz (IEEE Des. Test, 2015)

PPV-Based Modeling and Event-Driven Simulation of Injection-Locked Oscillators in SystemVerilog. - Ji-Eun Jang; Jaeha Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)