An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion. - Jeong-Don Ihm; Seung-Jun Bae; Kwang-Il Park; Ho-Young Song; Woo-Jin Lee; Hyun-Jin Kim; Kyoung-Ho Kim; Ho-Kyung Lee; Min-Sang Park; Sam-Young Bang; Mi-Jin Lee; Gil-Shin Moon; et al. (ISSCC, 2007)

A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips. - Ji-Hoon Lim; Jong-Chan Ha; Won-Young Jung; Yong-Ju Kim; Jae-Kyung Wee (IEICE Trans. Electron., 2007)

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion. - Seung-Jun Bae; Kwang-Il Park; Jeong-Don Ihm; Ho-Young Song; Woo-Jin Lee; Hyun-Jin Kim; Kyoung-Ho Kim; Yoon-Sik Park; Min-Sang Park; Hong-Kyong Lee; Sam-Young Bang; Gil-Shin Moon; et al. (IEEE J. Solid State Circuits, 2008)

A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction. - Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Min-Sang Park; Ji-Hoon Lim; Yong-Ki Cho; Dae-Hyun Kim 003; Dong-Min Kim; Hye-Ran Kim; Hyun-Joong Kim; Jin-Hyun Kim; Jin-Kook Kim; et al. (ISSCC, 2010)

A Seamless-Controlled Digital PLL Using Dual Loops for High Speed SoCs. - Young San Shin; Jae-Kyung Wee; Jong-Chan Ha; Ji-Hoon Lim; Yong-Ju Kim; Young-Sang Son (J. Circuits Syst. Comput., 2011)

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction. - Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Min-Sang Park; Ji-Hoon Lim; Yong-Ki Cho; Dae-Hyun Kim 003; Dong-Min Kim; Hye-Ran Kim; Hyun-Joong Kim; Jin-Hyun Kim; Jin-Kook Kim; et al. (IEEE J. Solid State Circuits, 2011)

One-chip multi-output SMPS using a shared digital controller and a pseudo relaxation oscillating technique. - Young-Kyun Park; Ji-Hoon Lim; Jae-Kyung Wee; Inchae Song (ISOCC, 2012)

A Digitally-Controlled SMPS Using a Novel High-Resolution DPWM Generator Based on a Pseudo Relaxation-Oscillation Technique. - Ji-Hoon Lim; Won-Young Jung; Yong-Ju Kim; Inchae Song; Jae-Kyung Wee (IEICE Trans. Electron., 2013)

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface. - Soo-Min Lee; Ji-Hoon Lim; Il-Min Yi; Young Jae Jang; Hae-Kang Jung; Kyunghoon Kim; Dae-Han Kwon; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2016)

A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs. - Ji-Hoon Lim; Jun-Hyun Bae; Jaemin Jang; Hae-Kang Jung; Hyunbae Lee; Yongju Kim; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Inductor Design of Interleaved Totem-Pole Bridgeless Boost PFC Based on Pareto Optimization. - Ye-Ji Hyeon; Dong-In Lee; Seong-Wook Jeong; Ji-Hoon Lim; Han-Shin Youn (IECON, 2023)

An Improved PWM Method of Inverter PFC for Non-Isolated OBC. - Dong-In Lee; Ye-Ji Hyeon; Seong-Wook Jeong; Ji-Hoon Lim; Han-Shin Youn; Youn-Sik Lee; Dae-woo Lee (IECON, 2023)

Differential Power Processing Converter With Active Clamp Structure and Integrated Planar Transformer for Power Generation Optimization of Multiple Photovoltaic Submodules. - Ji-Hoon Lim; Dong-In Lee; Ye-Ji Hyeon; Han-Shin Youn (IEEE Access, 2023)

A study on phenotype prediction using an artificial intelligence-based data augmentation approach. - Jiho Choi; Sung Woo Byun 001; Najeong Chae; Ji-Hoon Lim; Taehoon Lim; Hye In Lee; Hwa Seon Shin (IEEE Big Data, 2024)