Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology. - Charles H.-P. Wen; Li-C. Wang; Kwang-Ting Cheng; Wei-Ting Liu; Ji-Jan Chen (ITC, 2005)

On A Software-Based Self-Test Methodology and Its Application. - Charles H.-P. Wen; Li-C. Wang; Kwang-Ting Cheng; Kai Yang; Wei-Ting Liu; Ji-Jan Chen (VTS, 2005)

A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs. - Shih Ping Lin 001; Chung-Len Lee 001; Jwu E. Chen; Ji-Jan Chen; Kun-Lun Luo; Wen Ching Wu (ITC, 2006)

A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement. - Nai-Chen Daniel Cheng; Yu Lee; Ji-Jan Chen (ATS, 2007)

Diagnosis for MRAM write disturbance fault. - Chin-Lung Su; Chih-Wea Tsai; Cheng-Wen Wu; Ji-Jan Chen; Wen Ching Wu; Chien-Chung Hung; Ming-Jer Kao (ITC, 2007)

A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. - Shih-Ping Lin 001; Chung-Len Lee 001; Jwu-E Chen; Ji-Jan Chen; Kun-Lun Luo; Wen Ching Wu (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Experimental Results of Built-In Jitter Measurement for Gigahertz Clock. - Nai-Chen Daniel Cheng; Yu Lee; Ji-Jan Chen (ATS, 2008)

Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits. - Pei-Wen Luo; Jwu-E Chen; Chin-Long Wey; Liang-Chia Cheng; Ji-Jan Chen; Wen Ching Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A Test Integration Methodology for 3D Integrated Circuits. - Che-Wei Chou; Jin-Fu Li 001; Ji-Jan Chen; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (Asian Test Symposium, 2010)

An embedded wide-range and high-resolution CLOCK jitter measurement circuit. - Yu Lee; Ching-Yuan Yang; Nai-Chen Daniel Cheng; Ji-Jan Chen (DATE, 2010)

Diagnosis of MRAM Write Disturbance Fault. - Chin-Lung Su; Chih-Wea Tsai; Ching-Yi Chen; Wan-Yu Lo; Cheng-Wen Wu; Ji-Jan Chen; Wen Ching Wu; Chien-Chung Hung; Ming-Jer Kao (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Black-box leakage power modeling for cell library and SRAM compiler. - Chun-Kai Tseng; Shi-Yu Huang; Chia-Chien Weng; Shan-Chien Fang; Ji-Jan Chen (DATE, 2011)

A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. - Yu-Jen Huang; Jin-Fu Li 001; Ji-Jan Chen; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (VTS, 2011)

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. - Sergej Deutsch; Brion L. Keller; Vivek Chickermane; Subhasish Mukherjee; Navdeep Sood; Sandeep Kumar Goel; Ji-Jan Chen; Ashok Mehta; Frank Lee 004; Erik Jan Marinissen (ITC, 2012)

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. - Sandeep Kumar Goel; Saman Adham; Min-Jer Wang; Ji-Jan Chen; Tze-Chiang Huang; Ashok Mehta; Frank Lee 004; Vivek Chickermane; Brion L. Keller; Thomas Valind; Subhasish Mukherjee; Navdeep Sood; et al. (ITC, 2013)

Diagnosis and Layout Aware (DLA) Scan Chain Stitching. - Jing Ye 001; Yu Huang 005; Yu Hu 001; Wu-Tung Cheng; Ruifeng Guo; Liyang Lai; Ting-Pu Tai; Xiaowei Li 001; Wei-pin Changchien; Daw-Ming Lee; Ji-Jan Chen; Sandeep C. Eruvathi; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2015)