A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking. - Young-Ju Kim 001; Hye-Jung Kwon; Su-Yeon Doo; Yoon-Joo Eom; Young-Sik Kim; Min-Su Ahn; Yong-Hun Kim; Sang-Hoon Jung; Sung-Geun Do; Chang-Yong Lee; Jae-Sung Kim; Dong-Seok Kang; et al. (ISSCC, 2018)

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. - Hyung-Joon Chi; Chang-Kyo Lee; Junghwan Park; Jin-Seok Heo; Jaehoon Jung; Dongkeon Lee; Dae-Hyun Kim 003; Dukha Park; Kihan Kim; Sang-Yun Kim 001; Jinsol Park; Hyunyoon Cho; et al. (ISSCC, 2020)