Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology. - Weiwu Hu; Ji-Ye Zhao; Shi-Qiang Zhong; Xu Yang; Elio Guidetti; Chris Wu (J. Comput. Sci. Technol., 2007)

Register relocation to optimize clock network for multi-domain clock skew scheduling. - Liang Yang; Bao-Xia Fan; Ming Cong; Ji-Ye Zhao (ISCAS, 2010)

Physical Implementation of the 1GHz Godson-3 Quad-Core Microprocessor. - Bao-Xia Fan; Liang Yang; Jiang-Mei Wang; Ru Wang; Bin Xiao 006; Ying Xu; Dong Liu; Ji-Ye Zhao (J. Comput. Sci. Technol., 2010)

Physical Design Methodology for Godson-2G Microprocessor. - Ji-Ye Zhao; Dong Liu; Dan-Dan Huan; Meng-Hao Su; Bin Xiao; Ying Xu; Feng Shi; Chen Chen; Song Wang (J. Comput. Sci. Technol., 2010)