Power-aware pipelined multiplier design based on 2-dimensional pipeline gating. - Jia Di; Jiann-Shiun Yuan (ACM Great Lakes Symposium on VLSI, 2003)

High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders. - Jia Di; Jiann-Shiun Yuan; Ronald F. DeMara (ISVLSI, 2003)

Dynamic Active-bit Detection and Operands Exchange for Designing Energy-aware Asynchronous Multipliers. - Jiann-Shiun Yuan; Jia Di (CDES, 2005)

On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. - Jia Di; Parag K. Lala; Dilip P. Vasudevan (DFT, 2005)

D3L - A framework on fighting against non-invasive attacks to integrated circuits for security applications. - Jia Di; Fengwei Yang (Circuits, Signals, and Systems, 2005)

Teaching low-power electronic design in electrical and computer engineering. - Jiann-Shiun Yuan; Jia Di (IEEE Trans. Educ., 2005)

Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays. - Jia Di; Dilip P. Vasudevan (DELTA, 2006)

Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design. - Jia Di; Jiann-Shiun Yuan; Ronald F. DeMara (Integr., 2006)

Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuit Design. - Jia Di; Jiann-Shiun Yuan (J. Low Power Electron., 2006)

Reversible-logic design with online testability. - Dilip P. Vasudevan; Parag K. Lala; Jia Di; James Patrick Parkerson (IEEE Trans. Instrum. Meas., 2006)

Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems. - Jia Di; Parag K. Lala (J. Electron. Test., 2007)

Ownership Transfer of RFID Tags based on Electronic Fingerprint. - Senthilkumar Chinnappa Gounder Periaswamy; Dale R. Thompson; Jia Di (Security and Management, 2008)

Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power. - Andrew Bailey; Ahmad Al Zahrani; Guoyuan Fu; Jia Di; Scott C. Smith (J. Low Power Electron., 2008)

Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs. - Brent Hollosi; Tao Zhang 032; Ravi Sankar Parameswaran Nair; Yuan Xie 001; Jia Di; Scott C. Smith (3DIC, 2009)

Delay-Insensitive Ternary Logic. - Ravi Sankar Parameswaran Nair; Scott C. Smith; Jia Di (CDES, 2009)

Glitch-free design for multi-threshold CMOS NCL circuits. - Ahmad Al Zahrani; Andrew Bailey; Guoyuan Fu; Jia Di (ACM Great Lakes Symposium on VLSI, 2009)

Designing Asynchronous Circuits using NULL Convention Logic (NCL) - Scott C. Smith; Jia Di (Morgan & Claypool Publishers, 2009)

Delay-Insensitive Cell Matrix. - Scott C. Smith; David Roclin; Jia Di (CDES, 2010)

Analysis and Improvement of Delay-Insensitive Asynchronous Circuits Operating in Subthreshold Regime. - David Coleman; Jia Di (J. Low Power Electron., 2010)

Integrating Asynchronous Digital Design Into the Computer Engineering Curriculum. - Scott C. Smith; Waleed K. Al-Assadi; Jia Di (IEEE Trans. Educ., 2010)

A new topology for fully differential amplifiers that enhances their tolerance to external disturbances. - Guoyuan Fu; H. Alan Mantooth; Jia Di (ASICON, 2011)

A 12-bit CMOS current steering D/A converter with a fully differential voltage output. - Guoyuan Fu; H. Alan Mantooth; Jia Di (ISQED, 2011)

Fingerprinting RFID Tags. - Senthilkumar Chinnappa Gounder Periaswamy; Dale R. Thompson; Jia Di (IEEE Trans. Dependable Secur. Comput., 2011)

Feature selection for RFID tag identification. - Debrup Banerjee; Jiang Li 001; Jia Di; Dale R. Thompson (CHINACOM, 2012)

An efficient run-time encryption scheme for non-volatile main memory. - Xian Zhang 001; Chao Zhang 007; Guangyu Sun 003; Jia Di; Tao Zhang 032 (CASES, 2013)

An Asynchronous Advanced Encryption Standard Core Design for Energy Efficiency. - Michael Hinds; Brett Sparkman; Jia Di; Scott C. Smith (J. Low Power Electron., 2013)

Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic. - Washington Cilio; Michael Linder; Chris Porter; Jia Di; Dale R. Thompson; Scott C. Smith (Microelectron. J., 2013)

A comparative analysis of 3D-IC partitioning schemes for asynchronous circuits. - Landon Caley; Chien-Wei Lo; Francis Sabado; Jia Di (ICICDT, 2014)

Framework of an Adaptive Delay-Insensitive Asynchronous Platform for Energy Efficiency. - Liang Men; Brent Hollosi; Jia Di (ISVLSI, 2014)

An asynchronous finite impulse response filter design for Digital Signal Processing circuit. - Liang Men; Jia Di (MWSCAS, 2014)

Framework of a scalable delay-insensitive asynchronous platform enabling heterogeneous concurrency. - Liang Men; Jia Di (MWSCAS, 2014)

Exploiting hidden Markov models in identifying passive UHF RFID tags. - Baha' A. Alsaify; Dale R. Thompson; Jia Di (RWS, 2014)

Asynchronous Parallel Platforms with Balanced Performance and Energy. - Liang Men; Jia Di (J. Low Power Electron., 2014)

Teaching RFID Information Systems Security. - Dale R. Thompson; Jia Di; Michael K. Daugherty (IEEE Trans. Educ., 2014)

Investigation of obfuscation-based anti-reverse engineering for printed circuit boards. - Zimu Guo; Mark Tehranipoor; Domenic Forte; Jia Di (DAC, 2015)

Chip-level anti-reverse engineering using transformable interconnects. - Shuai Chen; Junlin Chen; Domenic Forte; Jia Di; Mark Tehranipoor; Lei Wang 003 (DFTS, 2015)

The effects of flooding attacks on time-critical communications in the smart grid. - Qinghua Li; Chase Ross; Jing Yang 002; Jia Di; Juan Carlos Balda; H. Alan Mantooth (ISGT, 2015)

Fork path: improving efficiency of ORAM by removing redundant memory accesses. - Xian Zhang 001; Guangyu Sun 003; Chao Zhang 007; Weiqi Zhang; Yun Liang 001; Tao Wang 004; Yiran Chen 001; Jia Di (MICRO, 2015)

Evaluating the capability and performance of access control policy verification tools. - Ang Li 005; Qinghua Li; Vincent C. Hu; Jia Di (MILCOM, 2015)

A novel PUF based on cell error rate distribution of STT-RAM. - Xian Zhang 001; Guangyu Sun 003; Yaojun Zhang; Yiran Chen 001; Hai Li 001; Wujie Wen; Jia Di (ASP-DAC, 2016)

Tracking Data Flow at Gate-Level through Structural Checking. - Thao Le 001; Jia Di; Mark Tehranipoor; Domenic Forte; Lei Wang 003 (ACM Great Lakes Symposium on VLSI, 2016)

Multi-threshold dual-spacer dual-rail delay-insensitive logic: An improved IC design methodology for side channel attack mitigation. - Jean Pierre T. Habimana; Francis Sabado; Jia Di (ISCAS, 2016)

Golden reference matching for gate-level netlist functionality identification. - Thao Le 001; Jia Di (MWSCAS, 2017)

Recent Advances in Low Power Asynchronous Circuit Design. - Jia Di; Brent A. Bell; William Bouillon; John Brady; Thao Le 001; Chien-Wei Lo; Liang Men; Spencer Nelson; Francis Sabado; Andrew Suchanek (J. Low Power Electron., 2017)

A SiC CMOS Digitally Controlled PWM Generator for High-Temperature Applications. - Sajib Roy; Robert C. Murphree; Affan Abbasi; Ashfaqur Rahman; Shamim Ahmed; James Austin Gattis; Matt Francis; Jim Holmes; H. Alan Mantooth; Jia Di (IEEE Trans. Ind. Electron., 2017)

Obfuscation-Based Protection Framework against Printed Circuit Boards Unauthorized Operation and Reverse Engineering. - Zimu Guo; Jia Di; Mark Tehranipoor; Domenic Forte (ACM Trans. Design Autom. Electr. Syst., 2017)

Hardware Trojan Detection and Functionality Determination for Soft IPs. - Thao Le 001; Lucas Weaver; Jia Di; Shaojie Zhang 001; Yier Jin (IVSW, 2018)

Comprehensive Comparison of NULL Convention Logic Threshold Gate Implementations. - Kelby Haulmark; Wassim Khalil; William Bouillon; Jia Di (NGCAS, 2018)

The Old Frontier of Reverse Engineering: Netlist Partitioning. - Travis Meade; Kaveh Shamsi; Thao Le 001; Jia Di; Shaojie Zhang 001; Yier Jin (J. Hardw. Syst. Secur., 2018)

Clockless Spintronic Logic: A Robust and Ultra-Low Power Computing Paradigm. - Yu Bai 004; Ronald F. DeMara; Jia Di; Mingjie Lin (IEEE Trans. Computers, 2018)

Hardware IP Classification through Weighted Characteristics. - Brendan McGeehan; Flora Smith; Thao Le 001; Hunter Nauman; Jia Di (HPEC, 2019)

Wireless Sensor Node Platform for In-Plant Stress Monitoring. - Affan Abbasi; Marvin W. Suggs; Logan Walz; Asma Mahar; Ayesha Hassan; Robert C. Murphree; Sajib Roy; Trenton L. Roberts; Jia Di; H. Alan Mantooth (IEEE SENSORS, 2020)

A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates. - Sreeja Chowdhury; Rabin Yu Acharya; William Boullion; Andrew Felder; Mark Howard; Jia Di; Domenic Forte (ITC, 2020)

Reducing Power Consumption in Asynchronous MTNCL Circuits through Selective Sleep. - Cole Sherrill; Michael Tennant; Jia Di (MWSCAS, 2020)

Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits. - Brett Sparkman; Scott C. Smith; Jia Di (VTS, 2020)

Fork Path: Batching ORAM Requests to Remove Redundant Memory Accesses. - Jingchen Zhu; Guangyu Sun 003; Xian Zhang 001; Chao Zhang 007; Weiqi Zhang; Yun Liang 001; Tao Wang 004; Yiran Chen 001; Jia Di (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Reconfigurable ASIC Implementation of Asynchronous Recurrent Neural Networks. - Spencer Nelson; Sang Yun Kim 002; Jia Di; Zhe Zhou 002; Zhihang Yuan; Guangyu Sun 003 (ASYNC, 2021)

Design of Asynchronous Polymorphic Logic Gates for Hardware Security. - Chandler Bernard; William Bryant; Richard Becker; Jia Di (HPEC, 2021)

Rapid Configuration of Asynchronous Recurrent Neural Networks for ASIC Implementations. - Spencer Nelson; Wassim Khalil; SangYun Kim 002; Jia Di; Zhe Zhou 002; Zhihang Yuan; Guang-Yu Sun 003 (HPEC, 2021)

Character Reassignment for Hardware Trojan Detection. - Noah Waller; Hunter Nauman; Derek Taylor; Rafael Del Carmen; Jia Di (MWSCAS, 2021)

Building Fast and Compact Sketches for Approximately Multi-Set Multi-Membership Querying. - Rundong Li 002; Pinghui Wang; Jiongli Zhu; Junzhou Zhao; Jia Di; Xiaofei Yang 003; Kai Ye 001 (SIGMOD Conference, 2021)

Using dummy data for RFID tag and reader authentication. - Baha' A. Alsaify; Dale R. Thompson; Abdallah Y. Alma'aitah; Jia Di (Digit. Commun. Networks, 2022)

Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism. - Brett Sparkman; Scott C. Smith; Jia Di (J. Electron. Test., 2022)

Use It-No Need to Shake It!: Accurate Implicit Authentication for Everyday Objects with Smart Sensing. - Chuxiong Wu; Xiaopeng Li 001; Fei Zuo; Lannan Luo; Xiaojiang Du; Jia Di; Qiang Zeng 001 (Proc. ACM Interact. Mob. Wearable Ubiquitous Technol., 2022)

An Internet of Things Testbed for Education and Community Research. - John Swaim; Chad Workman; Jia Di; Xiaojiang Du (AIBThings, 2023)

Case Study for Skewing MTNCL Circuits. - Cole Sherrill; Kyle Orman; Nicholas Brown; Jia Di (ASYNC, 2023)

Amnesiac Memory: A Self-Destructive Polymorphic Mechanism Against Cold Boot Data Remanence Attack. - Tasnuva Farheen; Sourav Roy; Andrew Cannon; Jia Di; Shahin Tajik; Domenic Forte (ACM Great Lakes Symposium on VLSI, 2024)

Calibratable Polymorphic Temperature Sensor for Detecting Fault Injection and Side-Channel Attacks. - Tasnuva Farheen; Sourav Roy; Jia Di; Shahin Tajik; Domenic Forte (HOST, 2024)

Hardware Trojan Detection Utilizing Graph Neural Networks and Structural Checking. - Hunter Nauman; Jia Di (HPEC, 2024)

TrustEvent: Cross-Platform IoT Trigger Event Verification Using Edge Computing. - Trent Reichenbach; Chenglong Fu 002; Xiaojiang Du; Jia Di; Yuede Ji (ICC, 2024)

Seeing Is Believing: Extracting Semantic Information from Video for Verifying IoT Events. - Chenglong Fu 002; Xiaojiang Du; Qiang Zeng 001; Zhenyu Zhao; Fei Zuo; Jia Di (WISEC, 2024)

Half-Xor: A Fully-Dynamic Sketch for Estimating the Number of Distinct Values in Big Tables. - Pinghui Wang; Dongdong Xie 004; Junzhou Zhao; Jinsong Li 004; Zhicheng Li; Rundong Li 002; Yang Ren; Jia Di (IEEE Trans. Knowl. Data Eng., 2024)

Synthesis and Timing Constraints for Reliable MTNCL Asynchronous Circuits. - Cole Sherrill; Ethan Brugger; Jia Di (ASYNC, 2025)

Innovations in MTNCL Gate Design: An Alternative MTCMOS Power-Gating Approach. - Cole Sherrill; Kile Harvey; Zhihan Weng; Jia Di (ASYNC, 2025)