Parallelizing SRAM arrays with customized bit-cell for binary neural networks. - Rui Liu 005; Xiaochen Peng; Xiaoyu Sun 001; Win-San Khwa; Xin Si; Jia-Jing Chen; Jia-Fang Li; Meng-Fan Chang; Shimeng Yu (DAC, 2018)

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. - Win-San Khwa; Jia-Jing Chen; Jia-Fang Li; Xin Si; En-Yu Yang; Xiaoyu Sun 001; Rui Liu 005; Pai-Yu Chen; Qiang Li 021; Shimeng Yu; Meng-Fan Chang (ISSCC, 2018)

A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors. - Cheng-Xin Xue; Wei-Hao Chen; Je-Syu Liu; Jia-Fang Li; Wei-Yu Lin; Wei-En Lin; Jing-Hong Wang; Wei-Chen Wei; Ting-Wei Chang; Tung-Cheng Chang; Tsung-Yuan Huang; Hui-Yao Kao; et al. (ISSCC, 2019)

A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors. - Xin Si; Win-San Khwa; Jia-Jing Chen; Jia-Fang Li; Xiaoyu Sun 001; Rui Liu 005; Shimeng Yu; Hiroyuki Yamauchi; Qiang Li 021; Meng-Fan Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors. - Cheng-Xin Xue; Ting-Wei Chang; Tung-Cheng Chang; Hui-Yao Kao; Yen-Cheng Chiu; Chun-Ying Lee; Ya-Chin King; Chrong Jung Lin; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Wei-Hao Chen; et al. (IEEE J. Solid State Circuits, 2020)