Jia Wang

Orcid: 0000-0002-6159-6085

Affiliations:
  • Illinois Institute of Technology, Department of Electrical and Computer Engineering, Chicago, IL, USA
  • Northwestern University, Electrical Engineering and Computer Science, Evanston, IL, USA (PhD 2008)


According to our database1, Jia Wang authored at least 22 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2023
GraphPlanner: Floorplanning with Graph Neural Network.
ACM Trans. Design Autom. Electr. Syst., March, 2023

2022
Floorplanning with graph attention.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2020
KNN-enhanced Deep Learning Against Noisy Labels.
CoRR, 2020

2013
Large-Scale Energy Storage System Design and Optimization for Emerging Electric-Drive Vehicles.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2010
Hybrid energy storage system integration for vehicles.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

iRetILP: an efficient incremental algorithm for min-period retiming under general delay model.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Gate Sizing by Lagrangian Relaxation Revisited.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Risk aversion min-period retiming under process variations.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Exploring adjacency in floorplanning.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Linear constraint graph for floorplan optimization with soft blocks.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

An efficient incremental algorithm for min-area retiming.
Proceedings of the 45th Design Automation Conference, 2008

2007
Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Unified Incremental Physical-Level and High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Address generation for nanowire decoders.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
Clustering for Processing Rate Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Processing Rate Optimization by Sequential System Floorplanning.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Optimal jumper insertion for antenna avoidance under ratio upper-bound.
Proceedings of the 43rd Design Automation Conference, 2006

TAPHS: thermal-aware unified physical-level and high-level synthesis.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Incremental exploration of the combined physical and behavioral design space.
Proceedings of the 42nd Design Automation Conference, 2005

Interconnect estimation without packing via ACG floorplans.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
ACG-Adjacent Constraint Graph for General Floorplans.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Minimal period retiming under process variations.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004


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