Minimal period retiming under process variations. - Jia Wang 003; Hai Zhou 001 (ACM Great Lakes Symposium on VLSI, 2004)

ACG-Adjacent Constraint Graph for General Floorplans. - Hai Zhou 001; Jia Wang 003 (ICCD, 2004)

Interconnect estimation without packing via ACG floorplans. - Jia Wang 003; Hai Zhou 001 (ASP-DAC, 2005)

Incremental exploration of the combined physical and behavioral design space. - Zhenyu (Peter) Gu; Jia Wang 003; Robert P. Dick; Hai Zhou 001 (DAC, 2005)

TAPHS: thermal-aware unified physical-level and high-level synthesis. - Zhenyu (Peter) Gu; Yonghong Yang; Jia Wang 003; Robert P. Dick; Li Shang (ASP-DAC, 2006)

Optimal jumper insertion for antenna avoidance under ratio upper-bound. - Jia Wang 003; Hai Zhou 001 (DAC, 2006)

Processing Rate Optimization by Sequential System Floorplanning. - Jia Wang 003; Hai Zhou 001; Ping-Chih Wu (ISQED, 2006)

Clustering for Processing Rate Optimization. - Chuan Lin 002; Jia Wang 003; Hai Zhou 001 (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Address generation for nanowire decoders. - Jia Wang 003; Ming-Yang Kao; Hai Zhou 001 (ACM Great Lakes Symposium on VLSI, 2007)

Unified Incremental Physical-Level and High-Level Synthesis. - Zhenyu (Peter) Gu; Jia Wang 003; Robert P. Dick; Hai Zhou 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing. - Jia Wang 003; Hai Zhou 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

An efficient incremental algorithm for min-area retiming. - Jia Wang 003; Hai Zhou 001 (DAC, 2008)

Linear constraint graph for floorplan optimization with soft blocks. - Jia Wang 003; Hai Zhou 001 (ICCAD, 2008)

Exploring adjacency in floorplanning. - Jia Wang 003; Hai Zhou 001 (ASP-DAC, 2009)

Risk aversion min-period retiming under process variations. - Jia Wang 003; Hai Zhou 001 (ASP-DAC, 2009)

Gate Sizing by Lagrangian Relaxation Revisited. - Jia Wang 003; Debasish Das; Hai Zhou 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

iRetILP: an efficient incremental algorithm for min-period retiming under general delay model. - Debasish Das; Jia Wang 003; Hai Zhou 001 (ASP-DAC, 2010)

Hybrid energy storage system integration for vehicles. - Jia Wang 003; Kun Li; Qin Lv; Hai Zhou 001; Li Shang (ISLPED, 2010)

Large-Scale Energy Storage System Design and Optimization for Emerging Electric-Drive Vehicles. - Jie Wu; Jia Wang 003; Kun Li; Hai Zhou 001; Qin Lv; Li Shang; Yihe Sun (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

KNN-enhanced Deep Learning Against Noisy Labels. - Shuyu Kong; You Li 008; Jia Wang 003; Amin Rezaei 001; Hai Zhou 001 (CoRR, 2020)

Floorplanning with graph attention. - Yiting Liu; Ziyi Ju; Zhengming Li; Mingzhi Dong; Hai Zhou 001; Jia Wang 003; Fan Yang 001; Xuan Zeng 001; Li Shang (DAC, 2022)

GraphPlanner: Floorplanning with Graph Neural Network. - Yiting Liu; Ziyi Ju; Zhengming Li; Mingzhi Dong; Hai Zhou 001; Jia Wang 003; Fan Yang 001; Xuan Zeng 001; Li Shang (ACM Trans. Design Autom. Electr. Syst., 2023)

The Power of Graph Signal Processing for Chip Placement Acceleration. - Yiting Liu; Hai Zhou 001; Jia Wang 003; Fan Yang 001; Xuan Zeng 001; Li Shang (ICCAD, 2024)

Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions. - Yiting Liu; Hai Zhou 001; Jia Wang 003; Fan Yang 001; Xuan Zeng 001; Li Shang (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Enhancing Modern SAT Solver With Machine Learning Method. - Guanting Chen; Jia Wang 003 (ACM Great Lakes Symposium on VLSI, 2025)