Assertion-based power/performance analysis of network processor architectures. - Jia Yu 008; Wei Wu 024; Xi Chen 024; Harry Hsieh; Jun Yang 002; Felice Balarin (HLDVT, 2004)

Low power network processor design using clock gating. - Yan Luo 001; Jia Yu 008; Jun Yang 002; Laxmi N. Bhuyan (DAC, 2005)

Assertion-Based Design Exploration of DVS in Network Processor Architectures. - Jia Yu 008; Wei Wu 024; Xi Chen 024; Harry Hsieh; Jun Yang 002; Felice Balarin (DATE, 2005)

Enhancing Network Processor Simulation Speed with Statistical Input Sampling. - Jia Yu 008; Jun Yang 002; Shaojie Chen; Yan Luo 001; Laxmi N. Bhuyan (HiPEAC, 2005)

A low energy cache design for multimedia applications exploiting set access locality. - Jun Yang 002; Jia Yu 008; Youtao Zhang (J. Syst. Archit., 2005)

Program Mapping onto Network Processors by Recursive Bipartitioning and Refining. - Jia Yu 008; Jingnan Yao; Laxmi N. Bhuyan; Jun Yang 002 (DAC, 2007)

Conserving network processor power consumption by exploiting traffic variability. - Yan Luo 001; Jia Yu 008; Jun Yang 002; Laxmi N. Bhuyan (ACM Trans. Archit. Code Optim., 2007)

Revisiting the Cache Effect on Multicore Multithreaded Network Processors. - Zhen Liu 018; Jia Yu 008; Xiaojun Wang 001; Bin Liu 001; Laxmi N. Bhuyan (DSD, 2008)

Experience on Applying Push Model to Packet Processors in High Performance Routers. - Bo Yuan 003; Hongbo Zhao; Chengchen Hu; Bin Liu 001; Jia Yu 008; Laxmi N. Bhuyan (GLOBECOM, 2010)

Improving the throughput and delay performance of network processors by applying push model. - Bin Liu 001; Bo Yuan 003; Huichen Dai; Hongbo Zhao; Jia Yu 008; Laxmi N. Bhuyan (IWQoS, 2012)