FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures. - Jiafeng Xie; Jianjun He; Guanzheng Tan (Microelectron. J., 2010)

Hardware Efficient Approach for Memoryless-Based Multiplication and Its Application to FIR Filter. - Jianjun He; Jiafeng Xie (J. Comput., 2011)

Low-latency area-delay-efficient systolic multiplier over GF(2m) for a wider class of trinomials using parallel register sharing. - Jiafeng Xie; Pramod Kumar Meher; Jianjun He (ISCAS, 2012)

Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic. - Jiafeng Xie; Pramod Kumar Meher; Jianjun He (IEEE Trans. Computers, 2013)

Low Latency Systolic Montgomery Multiplier for Finite Field $GF(2^{m})$ Based on Pentanomials. - Jiafeng Xie; Jianjun He; Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Low-Complexity Multiplier for GF(2m) Based on All-One Polynomials. - Jiafeng Xie; Pramod Kumar Meher; Jianjun He (IEEE Trans. Very Large Scale Integr. Syst., 2013)

FPGA design space exploration of IDEA cryptography IP core. - Dinesh Varma Penumetcha; Jiafeng Xie; Saiyu Ren (MWSCAS, 2015)

High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations. - Jiafeng Xie; Pramod Kumar Meher; Zhi-Hong Mao (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Low-Latency High-Throughput Systolic Multipliers Over GF(2m) for NIST Recommended Pentanomials. - Jiafeng Xie; Pramod Kumar Meher; Zhi-Hong Mao (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

High-Throughput Digit-Level Systolic Multiplier Over GF(2m) Based on Irreducible Trinomials. - Jiafeng Xie; Pramod Kumar Meher; Zhi-Hong Mao (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Error detection reliable architectures of Camellia block cipher applicable to different variants of its substitution boxes. - Mehran Mozaffari Kermani; Reza Azarderakhsh; Jiafeng Xie (AsianHOST, 2016)

Evaluating obfuscation performance of novel algorithm-to-architecture mapping techniques in systolic-array-based circuits. - Xiaojun Zhou; Jiafeng Xie (AsianHOST, 2017)

Efficient FPGA Implementation of Low-Complexity Systolic Karatsuba Multiplier Over GF(2m) Based on NIST Polynomials. - Jiafeng Xie; Pramod Kumar Meher; Mingui Sun; Yuecheng Li; Bo Zeng 001; Zhi-Hong Mao (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over $GF(2^{m})$ and Their Applications in Trinomial Multipliers. - Pingxiuqi Chen; Shaik Nazeem Basha; Mehran Mozaffari Kermani; Reza Azarderakhsh; Jiafeng Xie (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Low-Complexity Digit-Level Systolic Gaussian Normal Basis Multiplier. - Qiliang Shao; Zhenji Hu; Shaobo Chen; Pingxiuqi Chen; Jiafeng Xie (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Improving Fast Segmentation With Teacher-Student Learning. - Jiafeng Xie; Bing Shuai; Jianfang Hu; Jingyang Lin; Wei-Shi Zheng 001 (BMVC, 2018)

Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm. - Chiou-Yng Lee; Jiafeng Xie (ICCD, 2018)

Efficient Implementation of Karatsuba Algorithm Based Three-Operand Multiplication Over Binary Extension Field. - Chiou-Yng Lee; Chia-Chen Fan; Jiafeng Xie; Shyan-Ming Yuan (IEEE Access, 2018)

Novel Hybrid-Size Digit-Serial Systolic Multiplier over GF(2m). - Zhenji Hu; Jiafeng Xie (Symmetry, 2018)

Reliable Inversion in GF(28) With Redundant Arithmetic for Secure Error Detection of Cryptographic Architectures. - Mehran Mozaffari Kermani; Amir Jalali; Reza Azarderakhsh; Jiafeng Xie; Kim-Kwang Raymond Choo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over GF(2m). - Qiliang Shao; Zhenji Hu; Shaik Nazeem Basha; Zhiping Zhang; Zhiqiang Wu 001; Chiou-Yng Lee; Jiafeng Xie (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Low Register-Complexity Systolic Digit-Serial Multiplier Over GF(2m) Based on Trinomials. - Jiafeng Xie; Pramod Kumar Meher; Xiaojun Zhou; Chiou-Yng Lee (IEEE Trans. Multi Scale Comput. Syst., 2018)

Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity. - Jiafeng Xie; Chiou-Yng Lee (FPGA, 2019)

LSM: Novel Low-Complexity Unified Systolic Multiplier over Binary Extension Field. - Jiafeng Xie; Chiou-Yng Lee (ACM Great Lakes Symposium on VLSI, 2019)

High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over GF(2m) based on MSPB. - Chiou-Yng Lee; Jiafeng Xie (HOST, 2019)

Efficient Scalable Three Operand Multiplier Over GF(2^m) Based on Novel Decomposition Strategy. - Chiou-Yng Lee; Jiafeng Xie (ICCD, 2019)

Low-Complexity Systolic Multiplier for GF(2m) using Toeplitz Matrix-Vector Product Method. - Jiafeng Xie; Chiou-Yng Lee; Pramod Kumar Meher (ISCAS, 2019)

Predicting Future Instance Segmentation with Contextual Pyramid ConvLSTMs. - Jiangxin Sun; Jiafeng Xie; Jianfang Hu; Zihang Lin; Jianhuang Lai; Wenjun Zeng 001; Wei-Shi Zheng 001 (ACM Multimedia, 2019)

Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm. - Chiou-Yng Lee; Jiafeng Xie (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach. - Jeng-Shyang Pan 001; Chiou-Yng Lee; Anissa Sghaier; Zeghid Medien; Jiafeng Xie (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis. - Jiafeng Xie; Chiou-Yng Lee; Pramod Kumar Meher; Zhi-Hong Mao (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Efficient Subquadratic Space Complexity Digit-Serial Multipliers over GF(2m) based on Bivariate Polynomial Basis Representation. - Chiou-Yng Lee; Jiafeng Xie (ASP-DAC, 2020)

Special Session: The Recent Advance in Hardware Implementation of Post-Quantum Cryptography. - Jiafeng Xie; Kanad Basu; Kris Gaj; Ujjwal Guin (VTS, 2020)

Weibo-MEL, Wikidata-MEL and Richpedia-MEL: Multimodal Entity Linking Benchmark Datasets. - Xingchen Zhou; Peng Wang 004; Guozheng Li; Jiafeng Xie; Jiangheng Wu (CCKS, 2021)

Efficient Implementation of Finite Field Arithmetic for Binary Ring-LWE Post-Quantum Cryptography Through a Novel Lookup-Table-Like Method. - Jiafeng Xie; Pengzhou He; Wujie Wen (DAC, 2021)

CROP: FPGA Implementation of High-Performance Polynomial Multiplication in Saber KEM based on Novel Cyclic-Row Oriented Processing Strategy. - Jiafeng Xie; Pengzhou He; Chiou-Yng Lee (ICCD, 2021)

FEED: A Chinese Financial Event Extraction Dataset Constructed by Distant Supervision. - Guozheng Li; Peng Wang 004; Jiafeng Xie; Ruilong Cui; Zhenkai Deng (IJCKG, 2021)

Novel Low-Complexity Polynomial Multiplication Over Hybrid Fields for Efficient Implementation of Binary Ring-LWE Post-Quantum Cryptography. - Pengzhou He; Ujjwal Guin; Jiafeng Xie (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography. - Tianyou Bao; José Luis Imaña; Pengzhou He; Jiafeng Xie (CODES+ISSS, 2022)

HPMA-NTRU: High-Performance Polynomial Multiplication Accelerator for NTRU. - Pengzhou He; Yazheng Tu; Ayesha Khalid; Máire O'Neill; Jiafeng Xie (DFT, 2022)

Ultra Low-Complexity Implementation of Binary Ring-LWE based Post-Quantum Cryptography on FPGA Platform. - Jiafeng Xie; Pengzhou He; Tianyou Bao (FPGA, 2022)

Systolic Acceleration of Polynomial Multiplication for KEM Saber and Binary Ring-LWE Post-Quantum Cryptography. - Tianyou Bao; Pengzhou He; Jiafeng Xie (HOST, 2022)

HPMA-Saber: High-Performance Polynomial Multiplication Accelerator for KEM Saber. - Pengzhou He; Tianyou Bao; Yazheng Tu; Jiafeng Xie (ICCD, 2022)

FastRE: Towards Fast Relation Extraction with Convolutional Encoder and Improved Cascade Binary Tagging Framework. - Guozheng Li; Xu Chen; Peng Wang 004; Jiafeng Xie; Qiqing Luo (IJCAI, 2022)

Hardware Implementation of High-Performance Polynomial Multiplication for KEM Saber. - Yazheng Tu; Pengzhou He; Chiou-Yng Lee; Danai Chasaki; Jiafeng Xie (ISCAS, 2022)

Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor. - Chiou-Yng Lee; Medien Zeghid; Anissa Sghaier; Hassan Yousif Ahmed; Jiafeng Xie (IEEE Access, 2022)

Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator. - Benjamin J. Lucas; Ali Alwan; Marion Murzello; Yazheng Tu; Pengzhou He; Andrew J. Schwartz; David Guevara; Ujjwal Guin; Kyle Juretus; Jiafeng Xie (IEEE Comput. Archit. Lett., 2022)

Certificateless signature schemes in Industrial Internet of Things: A comparative survey. - Saddam Hussain; Syed Sajid Ullah; Ihsan Ali; Jiafeng Xie; Venkata N. Inukollu (Comput. Commun., 2022)

AFIA: ATPG-Guided Fault Injection Attack on Secure Logic Locking. - Yadi Zhong; Ayush Jain 002; M. Tanjidur Rahman; Navid Asadizanjani; Jiafeng Xie; Ujjwal Guin (J. Electron. Test., 2022)

High-Performance Polynomial Multiplication Hardware Accelerators for KEM Saber and NTRU. - Elizabeth Carter; Pengzhou He; Jiafeng Xie (IACR Cryptol. ePrint Arch., 2022)

Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography. - José Luis Imaña; Pengzhou He; Tianyou Bao; Yazheng Tu; Jiafeng Xie (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Efficient Hardware Implementation of Finite Field Arithmetic $AB+C$AB+C for Binary Ring-LWE Based Post-Quantum Cryptography. - Jiafeng Xie; Pengzhou He; Xiaofang Wang; José Luis Imaña (IEEE Trans. Emerg. Top. Comput., 2022)

Efficient Implementation of Ring-Binary-LWE-based Lightweight PQC Accelerator on the FPGA Platform. - Pengzhou He; Tianyou Bao; Yazheng Tu; Jiafeng Xie (FCCM, 2023)

PasCore: A Chinese Overlapping Relation Extraction Model Based on Global Pointer Annotation Strategy. - Peng Wang 004; Jiafeng Xie; Xiye Chen; Guozheng Li; Wei Li (IJCAI, 2023)

LOCS: LOw-Latency and ConStant-Timing Implementation of Fixed-Weight Sampler for HQC. - Pengzhou He; Yazheng Tu; Jiafeng Xie (ISCAS, 2023)

Novel Implementation of High-Performance Polynomial Multiplication for Unified KEM Saber based on TMVP Design Strategy. - Pengzhou He; Jiafeng Xie (ISQED, 2023)

Hardware-Implemented Lightweight Accelerator for Large Integer Polynomial Multiplication. - Pengzhou He; Yazheng Tu; Çetin Kaya Koç; Jiafeng Xie (IEEE Comput. Archit. Lett., 2023)

VMA: Divide-and-Conquer Vectorized Map Annotation System for Large-Scale Driving Scene. - Shaoyu Chen; Yunchi Zhang; Bencheng Liao; Jiafeng Xie; Tianheng Cheng; Wei Sui; Qian Zhang 009; Chang Huang; Wenyu Liu 001; Xinggang Wang (CoRR, 2023)

Efficient Hardware RNS Decomposition for Post-Quantum Signature Scheme FALCON. - Samuel Coulon; Pengzhou He; Tianyou Bao; Jiafeng Xie (IACR Cryptol. ePrint Arch., 2023)

Monocular Road Planar Parallax Estimation. - Haobo Yuan; Teng Chen; Wei Sui; Jiafeng Xie; Lefei Zhang; Yuan Li; Qian Zhang 009 (IEEE Trans. Image Process., 2023)

COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC. - Pengzhou He; Yazheng Tu; Tianyou Bao; Leonel Sousa; Jiafeng Xie (IEEE Trans. Very Large Scale Integr. Syst., 2023)

LEAP: Lightweight and Efficient Accelerator for Sparse Polynomial Multiplication of HQC. - Yazheng Tu; Pengzhou He; Çetin Kaya Koç; Jiafeng Xie (IEEE Trans. Very Large Scale Integr. Syst., 2023)

FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography. - Pengzhou He; Tianyou Bao; Jiafeng Xie; Moeness G. Amin (ACM Trans. Reconfigurable Technol. Syst., 2023)

KINA: Karatsuba Initiated Novel Accelerator for Ring-Binary-LWE (RBLWE)-Based Post-Quantum Cryptography. - Pengzhou He; Yazheng Tu; Jiafeng Xie; H. S. Jacinto (IEEE Trans. Very Large Scale Integr. Syst., 2023)

LAMP: Efficient Implementation of Lightweight Accelerator for Polynomial MultiPlication, From Falcon to RBLWE-ENC. - Pengzhou He; Ben Mongirdas; Çetin Kaya Koç; Jiafeng Xie (ACM Great Lakes Symposium on VLSI, 2024)

Invited Paper: Enhancing Privacy-Preserving Computing with Optimized CKKS Encryption: A Hardware Acceleration Approach. - Tianyou Bao; Pengzhou He; Jiafeng Xie (ICCAD, 2024)

HELP: Highly Efficient and Low-Latency Hardware Accelerator for Integer Polynomial Multiplication. - Pengzhou He; Tianyou Bao; Çetin Kaya Koç; Jiafeng Xie (ISVLSI, 2024)

SMALL: Scalable Matrix OriginAted Large Integer PoLynomial Multiplication Accelerator for Lattice-Based Post-Quantum Cryptography. - Jiafeng Xie; Pengzhou He; Samira Carolina Oliva Madrigal; Çetin Kaya Koç (WAIFI, 2024)

SCALES: SCALable and Area-Efficient Systolic Accelerator for Ternary Polynomial Multiplication. - Samuel Coulon; Tianyou Bao; Jiafeng Xie (IEEE Comput. Archit. Lett., 2024)

LTE: Lightweight and Time-Efficient Hardware Encoder for Post-Quantum Scheme HQC. - Yazheng Tu; Pengzhou He; Chip-Hong Chang; Jiafeng Xie (IEEE Comput. Archit. Lett., 2024)

FELIX (XGCD for FALCON): FPGA-based Scalable and Lightweight Accelerator for Large Integer Extended GCD. - Samuel Coulon; Tianyou Bao; Jiafeng Xie (IACR Cryptol. ePrint Arch., 2024)

CASA: A Compact and Scalable Accelerator for Approximate Homomorphic Encryption. - Pengzhou He; Samira Carolina Oliva Madrigal; Çetin Kaya Koç; Tianyou Bao; Jiafeng Xie (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024)

Hardware Circuits and Systems Design for Post-Quantum Cryptography - A Tutorial Brief. - Jiafeng Xie; Wenfeng Zhao; Hanho Lee; Debapriya Basu Roy; Xinmiao Zhang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

TINA: TMVP-Initiated Novel Accelerator for Lightweight Ring-LWE-Based PQC. - Tianyou Bao; Pengzhou He; Shi Bai 001; Jiafeng Xie (IEEE Trans. Very Large Scale Integr. Syst., 2024)

AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-Based Lightweight PQC. - Tianyou Bao; Pengzhou He; Jiafeng Xie; H. S. Jacinto (ACM Trans. Reconfigurable Technol. Syst., 2024)

FELIX: FPGA-Based Scalable and Lightweight Accelerator for Large Integer Extended GCD. - Samuel Coulon; Tianyou Bao; Jiafeng Xie (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Efficient Post-Quantum Cryptographic Hardware for Healthcare Applications. - Samuel Coulon; Tianyou Bao; Jiafeng Xie (ISCAS, 2025)

LTE: Lightweight and Timing-Efficient Unequal-Sized Polynomial Multiplication Accelerators. - Yazheng Tu; Tianyou Bao; Pengzhou He; Leonel Sousa; Jiafeng Xie (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

HSPA: High-Throughput Sparse Polynomial Multiplication for Code-based Post-Quantum Cryptography. - Pengzhou He; Yazheng Tu; Tianyou Bao; Çetin Çetin Koç; Jiafeng Xie (ACM Trans. Embed. Comput. Syst., 2025)

SCOPE: Schoolbook-Originated Novel Polynomial Multiplication Accelerators for NTRU-Based PQC. - Yazheng Tu; Shi Bai 001; Jinjun Xiong; Jiafeng Xie (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Measuring Computational Universality of Fully Homomorphic Encryption. - Jiaqi Xue; Xin Xin; Wei Zhang 056; Mengxin Zheng; Qianqian Song; Minxuan Zhou; Yushun Dong; Dongjie Wang; Xun Chen; Jiafeng Xie; Liqiang Wang; David Mohaisen; et al. (CoRR, 2025)

High-Performance Instruction-Set Hardware Accelerator for Ring-Binary-LWE-Based Lightweight PQC. - Pengzhou He; Tianyou Bao; Jiafeng Xie (IEEE Trans. Very Large Scale Integr. Syst., 2025)

CHIRP: Compact and High-Performance FPGA Implementation of Unified Hardware Accelerators for Ring-Binary-LWE-based PQC. - Tianyou Bao; Pengzhou He; Daisuke Fujimoto; Yuichi Hayashi; Jiafeng Xie (ACM Trans. Reconfigurable Technol. Syst., 2025)