A wearable system for cardiopulmonary assessment and personalized respiratory training. - Jiajia Cui; Zhipei Huang; Dina Jiaerken; Ye Fan; Shuxia Zhao; Lingyan Zhang; Jiankang Wu (Future Gener. Comput. Syst., 2020)

Automatic Detection of the Cyclic Alternating Pattern of Sleep and Diagnosis of Sleep-Related Pathologies Based on Cardiopulmonary Resonance Indices. - Jiajia Cui; Zhipei Huang; Jiankang Wu (Sensors, 2022)

A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology. - Xinhang Xu; Linxiao Shen; Siyuan Ye; Jiayi Wu; Zhuoyi Chen; Jihang Gao; Jiajia Cui; Yihan Zhang 002; Ru Huang 001; Le Ye (ESSCIRC, 2023)

A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing. - Peiyu Chen; Meng Wu 005; Wentao Zhao; Jiajia Cui; Zhixuan Wang; Yadong Zhang; Qijun Wang; Jiayoon Ru; Linxiao Shen; Tianyu Jia; Yufei Ma 002; Le Ye; et al. (ISSCC, 2023)

A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting. - Jihang Gao; Linxiao Shen; Heyi Li; Siyuan Ye; Jie Li; Xinhang Xu; Jiajia Cui; Yunhung Gao; Ru Huang 001; Le Ye (ISSCC, 2023)

User behavior-based semi-supervised network service host threat detection. - Fuxi Wang; Jiajia Cui; Jun Yang; Xianggen Wang; Biao Leng (ITCC, 2023)

An 8b 1GS/s SAR ADC with Metastability-Based Resolution/Speed Enhancement and Self-Tuning Delay Achieving 47.2dB SNDR at Nyquist Input. - Jie Li; Linxiao Shen; Siyuan Ye; Jihang Gao; Jiajia Cui; Xinhang Xu; Zhuoyi Chen; Yaohui Luan; Yuanxin Bao; Ru Huang 001; Le Ye (CICC, 2024)

9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique. - Zhuoyi Chen; Linxiao Shen; Siyuan Ye; Jihang Gao; Jie Li; Jiajia Cui; Xinhang Xu; Yaohui Luan; Hao Zhang 119; Le Ye; Ru Huang 001 (ISSCC, 2024)

3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS. - Xinhang Xu; Siyuan Ye; Yaohui Luan; Jihang Gao; Jie Li; Jiajia Cui; Hao Zhang 119; Ru Huang 001; Linxiao Shen; Le Ye (ISSCC, 2024)

9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting. - Siyuan Ye; Linxiao Shen; Jihang Gao; Jie Li; Zhuoyi Chen; Xinhang Xu; Jiajia Cui; Hao Zhang 119; Xing Zhang 002; Le Ye; Ru Huang 001 (ISSCC, 2024)

A 110µW 99.5dB-SNDR 20kHz-BW Intrinsically Linear CTDSM with Hybrid Gm-Boosting OTA and Tri-Level FIR DACs. - Xinhang Xu; Yaohui Luan; Jie Li; Jihang Gao; Kwok Cheong Li; Jiajia Cui; Ru Huang 001; Linxiao Shen (CICC, 2025)

An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input-Buffer-Sampling Scheme and Fast Robust Background Inter-Stage Gain Calibration. - Zhuoyi Chen; Siyuan Ye; Jihang Gao; Jie Li; Jiajia Cui; Xinhang Xu; Yaohui Luan; Ru Huang 001; Linxiao Shen (ISSCC, 2025)

18.3: A 93.3dB SNDR, 180.4dB FoMs Calibration-Free Noise-Shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch-Error-Shaping Technique and Negative-R-Assisted Residue Integrator. - Jihang Gao; Yaohui Luan; Siyuan Ye; Xinhang Xu; Zhuoyi Chen; Jiajia Cui; Ru Huang 001; Linxiao Shen (ISSCC, 2025)

18.2 A 12.2μW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD ΔΣM with Gain-Embedded Bootstrapped Sampler. - Yaohui Luan; Xinhang Xu; Jihang Gao; Jiajia Cui; Zhuoyi Chen; Siyuan Ye; Ru Huang 001; Linxiao Shen (ISSCC, 2025)

18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting. - Siyuan Ye; Jiajia Cui; Jihang Gao; Jie Li; Xing Zhang 002; Ru Huang 001; Linxiao Shen (ISSCC, 2025)

An Energy-Efficient, High-Resolution kT/C-Noise- Canceled Pipelined-SAR Capacitance-to-Digital Converter With Incomplete-Settling-Based Correlated Level Shifting in 22-nm CMOS. - Jihang Gao; Siyuan Ye; Jie Li; Xinhang Xu; Zhuoyi Chen; Jiajia Cui; Yaohui Luan; Ru Huang 001; Le Ye; Linxiao Shen (IEEE J. Solid State Circuits, 2025)

A Flying-Capacitor-Based Reset Scheme for Low Power Dynamic Comparator. - Kwok Cheong Li; Xinhang Xu; Jihang Gao; Siyuan Ye; Jiajia Cui; Yacong Zhang; Ru Huang 001; Linxiao Shen (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A 2-mW 70.7-dB SNDR 200-MS/s Pipelined-SAR ADC Using Continuous-Time SAR-Assisted Detect-and-Skip and Open-Then-Close Correlated Level Shifting. - Siyuan Ye; Jihang Gao; Jie Li; Zhuoyi Chen; Xinhang Xu; Jiajia Cui; Yaohui Luan; Le Ye; Xing Zhang 002; Ru Huang 001; Linxiao Shen (IEEE J. Solid State Circuits, 2025)