Optimization of overdrive signoff. - Tuck-Boon Chan; Andrew B. Kahng; Jiajia Li 002; Siddhartha Nath (ASP-DAC, 2013)

Reliability-constrained die stacking order in 3DICs under manufacturing variability. - Tuck-Boon Chan; Andrew B. Kahng; Jiajia Li 002 (ISQED, 2013)

Toward quantifying the IC design value of interconnect technology improvements. - Tuck-Boon Chan; Andrew B. Kahng; Jiajia Li 002 (SLIP, 2013)

A new methodology for reduced cost of resilience. - Andrew B. Kahng; Seokhyeong Kang; Jiajia Li 002 (ACM Great Lakes Symposium on VLSI, 2014)

Horizontal benchmark extension for improved assessment of physical CAD research. - Andrew B. Kahng; Hyein Lee 001; Jiajia Li 002 (ACM Great Lakes Symposium on VLSI, 2014)

NOLO: A no-loop, predictive useful skew methodology for improved timing in IC implementation. - Tuck-Boon Chan; Andrew B. Kahng; Jiajia Li 002 (ISQED, 2014)

A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction. - Kwangsoo Han; Jiajia Li 002; Andrew B. Kahng; Siddhartha Nath; Jongpil Lee (DAC, 2015)

Optimizing Stochastic Circuits for Accuracy-Energy Tradeoffs. - Armin Alaghi; Wei-Ting Jonas Chan; John P. Hayes; Andrew B. Kahng; Jiajia Li 002 (ICCAD, 2015)

Mixed Cell-Height Implementation for Improved Design Quality in Advanced Nodes. - Sorin Dobre; Andrew B. Kahng; Jiajia Li 002 (ICCAD, 2015)

An Improved Methodology for Resilient Design Implementation. - Andrew B. Kahng; Seokhyeong Kang; Jiajia Li 002; José Pineda de Gyvez (ACM Trans. Design Autom. Electr. Syst., 2015)

Optimization of Overdrive Signoff in High-Performance and Low-Power ICs. - Tuck-Boon Chan; Andrew B. Kahng; Jiajia Li 002; Siddhartha Nath; Bongil Park (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Comprehensive optimization of scan chain timing during late-stage IC implementation. - Kun Young Chung; Andrew B. Kahng; Jiajia Li 002 (DAC, 2016)

Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stacking. - Kwangsoo Han; Andrew B. Kahng; Jiajia Li 002 (DATE, 2016)

Measuring progress and value of IC implementation technology. - Andrew B. Kahng; Hyein Lee 001; Jiajia Li 002 (ICCAD, 2016)

Improved flop tray-based design implementation for power reduction. - Andrew B. Kahng; Jiajia Li 002; Lutong Wang (ICCAD, 2016)

Floorplan and placement methodology for improved energy reduction in stacked power-domain design. - Kristof Blutman; Hamed Fatemi; Andrew B. Kahng; Ajay Kapoor; Jiajia Li 002; José Pineda de Gyvez (ASP-DAC, 2017)

Revisiting 3DIC benefit with multiple tiers. - Wei-Ting Jonas Chan; Andrew B. Kahng; Jiajia Li 002 (Integr., 2017)

Trading Accuracy for Energy in Stochastic Circuit Design. - Armin Alaghi; Wei-Ting Jonas Chan; John P. Hayes; Andrew B. Kahng; Jiajia Li 002 (ACM J. Emerg. Technol. Comput. Syst., 2017)

Logic Design Partitioning for Stacked Power Domains. - Kristof Blutman; Hamed Fatemi; Ajay Kapoor; Andrew B. Kahng; Jiajia Li 002; José Pineda de Gyvez (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Improved Physical Design and Signoff Methodologies for Better Integrated Circuit Design Quality - Jiajia Li 002 (2017)

Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes. - Sorin Dobre; Andrew B. Kahng; Jiajia Li 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

PROBE: A Placement, Routing, Back-End-of-Line Measurement Utility. - Alex Kahng; Andrew B. Kahng; Hyein Lee 001; Jiajia Li 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Enhancing sensitivity-based power reduction for an industry IC design context. - Hamed Fatemi; Andrew B. Kahng; Hyein Lee 001; Jiajia Li 002; José Pineda de Gyvez (Integr., 2019)

Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution. - Kwangsoo Han; Andrew B. Kahng; Jiajia Li 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)