Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. - Shobha Vasudevan; Jacob A. Abraham; Vinod Viswanath; Jiajin Tu (MEMOCODE, 2006)

Hardware Efficient Piecewise Linear Branch Predictor. - Jiajin Tu; Jian Chen 030; Lizy K. John (VLSI Design, 2007)

Sequential equivalence checking between system level and RTL descriptions. - Shobha Vasudevan; Vinod Viswanath; Jacob A. Abraham; Jiajin Tu (Des. Autom. Embed. Syst., 2008)

DaVinci: A Scalable Architecture for Neural Network Computing. - Heng Liao; Jiajin Tu; Jing Xia; Xiping Zhou (Hot Chips Symposium, 2019)

Ascend: a Scalable and Unified Architecture for Ubiquitous Deep Neural Network Computing : Industry Track Paper. - Heng Liao; Jiajin Tu; Jing Xia; Hu Liu; Xiping Zhou; Honghui Yuan; Yuxing Hu (HPCA, 2021)