Multifunction RNS modulo (2n±1) multipliers based on modified booth encoding. - Tso-Bing Juang; Jian-Hao Huang (APCCAS, 2012)

Multifunction RNS Modulo 2n ± 1 Multipliers. - Tso-Bing Juang; Chao-Tsung Kuo; Go-Long Wu; Jian-Hao Huang (J. Circuits Syst. Comput., 2012)

DVFS-aware motion estimation design scheme based on bandwidth-rate-distortion optimization in application processor systems. - Jui-Hung Hsieh; Jian-Hao Huang; Hung-Ren Wang (Integr., 2017)

DI-SSD: Desymmetrized interconnection architecture and dynamic timing calibration for solid-state drives. - Jian-Hao Huang; Ren-Shuo Liu (ASP-DAC, 2018)

A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array. - Pin-Yi Li; Cheng-Han Yang; Wei-Hao Chen; Jian-Hao Huang; Wei-Chen Wei; Je-Syu Liu; Wei-Yu Lin; Tzu-Hsiang Hsu; Chih-Cheng Hsieh; Ren-Shuo Liu; Meng-Fan Chang; Kea-Tiong Tang (BioCAS, 2018)

Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN). - Yun-Chen Lo; Yu-Chun Kuo; Yun-Sheng Chang; Jian-Hao Huang; Jun-Shen Wu; Wen-Chien Ting; Tai-Hsing Wen; Ren-Shuo Liu (ESSCIRC, 2019)