Design Consideration of 6.25 Gbps Signaling for High-Performance Server. - Jian Hong Jiang; Weixin Gai; Akira Hattori; Yasuo Hidaka; Takeshi Horie; Yoichi Koyanagi; Hideki Osone (ASP-DAC, 2007)

A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control. - Yasuo Hidaka; Weixin Gai; Takeshi Horie; Jian Hong Jiang; Yoichi Koyanagi; Hideki Osone (ISSCC, 2009)

A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control. - Yasuo Hidaka; Weixin Gai; Takeshi Horie; Jian Hong Jiang; Yoichi Koyanagi; Hideki Osone (IEEE J. Solid State Circuits, 2009)

A DC-46Gb/s 2: 1 multiplexer and source-series terminated driver in 20nm CMOS technology. - Jian Hong Jiang; Samir Parikh; Mark Lionbarger; Nikola Nedovic; Takuji Yamamoto (A-SSCC, 2014)

A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects. - Akinori Hayakawa; Masaya Kibune; Asako Toda; Shinsuke Tanaka; Takasi Simoyama; Yanfei Chen; Tomoyuki Akiyama; Shigekazu Okumura; Takeshi Baba; Tomoyuki Akahoshi; Seiji Ueno; Kazunori Maruyama; et al. (OFC, 2015)