The embedded SCR NMOS and low capacitance ESD protection device. - Jian-Hsing Lee; Yi-Hsun Wu; K. R. Peng; R. Y. Chang; Talee Yu; Tong-Chern Ong (CICC, 2002)

A new pre-driver design for improving the ESD performance of the high voltage tolerant I/O. - Jian-Hsing Lee; Jiaw-Ren Shih; Yi-Hsun Wu; Kuo-Feng Yu; Tong-Chern Ong (ISCAS (2), 2005)

Robust ESD self-protected LDNMOSFET by an enhanced displacement-current triggering. - Tzu-Cheng Kao; Chen-Hsin Lien; Chien-Wei Chiu; Jian-Hsing Lee; Yen-Hsiang Lo; Chung-Yu Hung; Tsung-Yi Huang; Hung-Der Su (IRPS, 2015)

Enhanced CDM-robustness for the packaged IC with the extra bonding wire to the die-attach plate. - Tzu-Cheng Kao; Jian-Hsing Lee; Chen-Hsin Lien; Chih-Hsien Wang; Kuang-Cheng Tai; Hung-Der Su (IRPS, 2015)

Methodology to achieve planar technology-like ESD performance in FINFET process. - Jian-Hsing Lee; Manjunatha Prabhu; Konstantin Korablev; Jagar Singh; Mahadeva Iyer Natarajan; Shesh Mani Pandey (IRPS, 2015)

Printed-circuit board (PCB) charge induced product yield-loss during the final test. - Jian-Hsing Lee; Kunihiko Takahashi; Manjunatha Prabhu; Mahadeva Iyer Natarajan (IRPS, 2015)

Analyzing Gate-Driven Circuit Parameters for Adding ESD Performances. - Shao-Chang Huang; Chih-Cherng Liao; Hsien-Feng Liao; Shou-Peng Weng; Karuna Nidhi; Yu-Kai Wang; Yi-Jen Chen; Hwa-Chyi Chiou; Yeh-Ning Jou; Jian-Hsing Lee (ICCE-TW, 2019)

Tunable Holding-Voltage High Voltage ESD Devices. - Jian-Hsing Lee; Natarajan Mahadeva Iyer (IRPS, 2019)

Physical Model for ESD Human Body Model to Transmission Line Pulse. - Jian-Hsing Lee; Natarajan Mahadeva Iyer; Timothy J. Maloney (IRPS, 2019)

The Correlations between ESD and TLP in Large Array Devices. - Shao-Chang Huang; Ching-Ho Li; Li-Fan Chen; Chun-Chih Chen; Ting-You Lin; Kai-Chieh Hsu; Gong-Kai Lin; Jian-Hsing Lee; Yu-Yung Kao; Ke-Horng Chen (ICCE-TW, 2020)

Signal Control Switching for Improving Large Array Devices' ESD Performances. - Shao-Chang Huang; Ching-Ho Li; Li-Fan Chen; Chun-Chih Chen; Ting-You Lin; Kai-Chieh Hsu; Gong-Kai Lin; Chih-Hsuan Lin; Jian-Hsing Lee; Yu-Yung Kao; Ke-Horng Chen (ICCE-TW, 2020)

Signal Control Switching Applied on Large Array Devices' Layouts. - Shao-Chang Huang; Yu-Yung Kao; Ching-Ho Li; Li-Fan Chen; Chun-Chih Chen; Kai-Chieh Hsu; Gong-Kai Lin; Jian-Hsing Lee; Ke-Horng Chen (ICCE-TW, 2021)

Optimizing Power IC Layouts by Simulation Tools. - Shao-Chang Huang; Ching-Ho Li; Li-Fan Chen; Chun-Chih Chen; Kai-Chieh Hsu; Gong-Kai Lin; Jian-Hsing Lee (ICCE-TW, 2021)

Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-µm BCD Process. - Chao-Yang Chen; Jian-Hsing Lee; Karuna Nidhi; Tzer-Yaa Bin; Geeng-Lih Lin; Ming-Dou Ker (IRPS, 2021)

Gate Voltages Impacting on Latch-up Measurements. - Shao-Chang Huang; Jian-Hsing Lee; Chun-Chih Chen; Ching-Ho Li; Chih-Cherng Liao; Kai-Chieh Hsu; Gong-Kai Lin; Li-Fan Chen; Chien-Wei Wang; Chih-Hsuan Lin; Yeh-Ning Jou; Ke-Horng Chen (ICCE-TW, 2022)

EOS Endurance Power Circuits without Depletion Mode Devices. - Shao-Chang Huang; Jian-Hsing Lee; Ching-Ho Li; Sue-Yi Chen; Chih-Hsuan Lin; Chun-Chih Chen; Li-Fan Chen; Gong-Kai Lin; Chien-Wei Wang; Kai-Chieh Hsu; Szu-Chi Chen; Shang-Chuan Pai; et al. (ICCE-TW, 2022)

Incorporation of a Simple ESD Circuit in a 650V E-Mode GaN HEMT for All-Terminal ESD Protection. - Jian-Hsing Lee; Yeh-Jen Huang; Li-Yang Hong; Li-Fan Chen; Yeh-Ning Jou; Shin-Cheng Lin; Walter Wohlmuth; Chih-Cherng Liao; Ching-Ho Li; Shoa-Chang Huang; Ke-Horng Chen (IRPS, 2022)

Bipolar Transistors' Holding Phenomena. - Shao-Chang Huang; Kai-Chieh Hsu; Chih-Hsuan Lin; Chien-Wei Wang; Ching-Ho Li; Chih-Cherng Liao; Jung-Tsun Chuang; Gong-Kai Lin; Lin-Fan Chen; Chun-Chih Chen; Yeh-Ning Jou; Jian-Hsing Lee; et al. (ICCE-Taiwan, 2023)

Optimizing Device Metal Routing Layouts by the Simulation Tool. - Shao-Chang Huang; Ching-Ho Li; Chih-Cherng Liao; Jung-Tsun Chuang; Chien-Wei Wang; Gong-Kai Lin; Lin-Fan Chen; Chun-Chih Chen; Kuan-I Ho; Che-Hua Chang; Hsiao-Ying Yang; Chung-Ren Lao; et al. (ICCE-Taiwan, 2023)

Transmission Line Pulse Width Impacting on Device Performances. - Shao-Chang Huang; Chien-Wei Wang; Chih-Hsuan Lin; Kai-Chieh Hsu; Ching-Ho Li; Chih-Cherng Liao; Jung-Tsun Chuang; Gong-Kai Lin; Lin-Fan Chen; Chun-Chih Chen; Yeh-Ning Jou; Jian-Hsing Lee; et al. (ICCE-Taiwan, 2023)

A Concise Electrothermal Model to Characterize the Thermal Safe-Operating Area of Power Transistor. - Jian-Hsing Lee; Gong-Kai Lin; Chun-Chih Chen; Li-Fan Chen; Chien-Wei Wang; Shao-Chang Huang; Ching-Ho Li; Chih-Cherng Liao; Jung-Tsun Chuang; Ke-Horng Chen (IRPS, 2023)

The Influence of the Block Design on the ID-VD Curves of Power Transistor for E-SOA Characterization. - Chun-Chih Chen; Shih-Chieh Chien; Chien-Wei Wang; Yu-Sheng Chiu; Jung-Tsun Chuang; Li-Fan Chen; Chieh-Yao Chuang; Jian-Hsing Lee (ICCE-Taiwan, 2024)

Negative Triggering Current Induced the Latch-up in the Circuit without the ESD device to Power. - Yeh-Jen Huang; Li-Yang Hong; Yeh-Ning Jou; Jian-Hsing Lee (ICCE-Taiwan, 2024)