A Supply Noise Compensation Circuit for Clock Buffers to Reduce Timing Jitter. - Jing Li 022; Jian Luo 004; Yongfeng Ding; Ning Ning 002 (APCCAS, 2018)

The Effects of Comparator Dynamic Capacitor Mismatch in SAR ADC and Correction. - Jian Luo 004; Jing Li 022; Ning Ning 002; Yang Liu 062; Qi Yu 002 (IEEE Access, 2018)

A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS. - Jian Luo 004; Jing Li 022; Ning Ning 002; Yang Liu 062; Qi Yu 002 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Low Voltage 10-Bit Non-Binary 2B/Cycle Time and Voltage Based SAR ADC. - Jian Luo 004; Jing Li 022; Ning Ning 002; Kejun Wu; Zhen Liu 013; Yang Liu 062; Qi Yu 002 (ISCAS, 2019)

A Full-Band Timing Mismatch Calibration Technique in Time-Interleaved ADCs. - Jing Li 022; Xin Ye; Jian Luo 004; Ning Ning 002; Qi Yu 002 (J. Circuits Syst. Comput., 2019)

A Bandwidth Mismatch Optimization Technique in Time-Interleaved Analog-to-Digital Converters. - Jian Luo 004; Jing Li 022; Shuangyi Wu; Ning Ning 002; Yang Liu 062 (J. Circuits Syst. Comput., 2019)

A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR ADC. - Jian Luo 004; Yang Liu 062; Jing Li 022; Ning Ning 002; Kejun Wu; Zhen Liu 013; Qi Yu 002 (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)