Global routing and track assignment for flip-chip designs. - Xiaodong Liu 018; Yifan Zhang; Gary K. Yeap; Chunlei Chu; Jian Sun 005; Xuan Zeng 001 (DAC, 2010)

Low power discrete voltage assignment under clock skew scheduling. - Li Li 021; Jian Sun 005; Yinghai Lu; Hai Zhou 001; Xuan Zeng 001 (ASP-DAC, 2011)

Post-routing layer assignment for double patterning. - Jian Sun 005; Yinghai Lu; Hai Zhou 001; Xuan Zeng 001 (ASP-DAC, 2011)

Post-routing layer assignment for double patterning with timing critical paths consideration. - Jian Sun 005; Yinghai Lu; Hai Zhou 001; Changhao Yan; Xuan Zeng 001 (Integr., 2013)