Jian Wang

According to our database1, Jian Wang authored at least 13 papers between 2009 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2014
Low Overhead Memory Subsystem Design for a Multicore Parallel DSP Processor.
PhD thesis, 2014

2013
Application Specific Instruction Set DSP Processors.
, 2013

Conflict-free data access for multi-bank memory architectures using padding.
Proceedings of the 20th Annual International Conference on High Performance Computing, 2013

ePUMA: A unique memory access based parallel DSP processor for SDR and CR.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013

2012
Automatic Permutation for Arbitrary Static Access Patterns.
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

Convolutional Decoding on Deep-pipelined SIMD Processor with Flexible Parallel Memory.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
An Efficient Streaming Star Network for Multi-core Parallel DSP Processor.
Proceedings of the Second International Conference on Networking and Computing, 2011

A multi-level arbitration and topology free streaming network for chip multiprocessor.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

ePUMA embedded parallel DSP processor with Unique Memory Access.
Proceedings of the 8th International Conference on Information, 2011

2010
Parallel Programming and Its Architectures Based on Data Access Separated Algorithm Kernels.
IJERTCS, 2010

Architectural Support for Reducing Parallel Processing Overhead in an Embedded Multiprocessor.
Proceedings of the IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, 2010

Software Programmable Data Allocation in Multi-bank Memory of SIMD Processors.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Large Matrix Multiplication on a Novel Heterogeneous Parallel DSP Architecture.
Proceedings of the Advanced Parallel Processing Technologies, 8th International Symposium, 2009


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