Research on design method of scalable Configurable IP Core. - Lei Li; Jian Wang 036; Yuan Wang; Jinmei Lai 001 (AHS, 2011)

FPGA interconnect timing library based on the statistical method. - Xiangzhi Meng; Liguang Chen; Hao Zhou 008; Jian Wang 036; Meng Yang 013; Jinmei Lai 001 (ASICON, 2011)

The design and verification of SEU-hardened configurable DFF. - Xinrui Zhang; Liguang Chen; Liyun Wang; Jian Wang 036; Jinmei Lai 001 (ASICON, 2011)

Weight-based FPGA placement algorithm with wire effect considered. - Huagang Li; Jian Wang 036; Jinmei Lai 001 (ASICON, 2013)

Improved unified interconnect unit for high speed and scalable FPGA. - Lei Li; Jian Wang 036; Jinmei Lai 001 (ASICON, 2013)

The timing control design of 65nm block RAM in FPGA. - Xinrui Zhang; Jian Wang 036; Dan Chen; Jinmei Lai 001; Lichun Bao; Xueling Liu (ASICON, 2013)

A novel multithread routing method for FPGAs (abstract only). - Chun Zhu; Qiuli Li; Jian Wang 036; Jinmei Lai 001 (FPGA, 2013)

A novel net-partition-based multithread FPGA routing method. - Chun Zhu; Jian Wang 036; Jinmei Lai 001 (FPL, 2013)

Novel FPGA clock network with low latency and skew (abstract only). - Lei Li; Jian Wang 036; Jinmei Lai 001 (FPGA, 2014)

A FPGA prototype design emphasis on low power technique. - Hanyang Xu; Jian Wang 036; Meilai Jin (FPGA, 2014)

FPGA bitstream compression and decompression based on LZ77 algorithm and BMC technique. - Yuanpei Gao; Haijiang Ye; Jian Wang 036; Jinmei Lai 001 (ASICON, 2015)

A power efficient current-mode differential driver for FPGAs. - Yuanlong Xiao; Jian Wang 036; Jinmei Lai 001 (ASICON, 2015)

A new automatic method for testing interconnect resources in FPGAs based on general routing matrix. - Zhen Yang; Chuanzeng Liang; Jian Wang 036; Jinmei Lai 001 (IEICE Electron. Express, 2015)

Testing FPGA Local Interconnects Based on Repeatable Configuration Modules (Abstract Only). - Zhen Yang; Jian Wang 036; Meng Yang 013; Jinmei Lai 001 (FPGA, 2016)

A universal automatic on-chip measurement of FPGA's internal setup and hold times. - Yuanlong Xiao; Jian Wang 036; Jinmei Lai 001 (IEICE Electron. Express, 2016)

Prototyping design of a flexible DSP block with pipeline structure for FPGA. - Hanyang Xu; Jian Wang 036; Jinmei Lai 001 (IEICE Electron. Express, 2016)

Remote embedded simulation system for SW/HW co-design based on dynamic partial reconfiguration. - Jiaqi Gu; Ruoyao Wang; Jian Wang 036; Jinmei Lai 001; Qinghua Duan (ASICON, 2017)

A deep research on the chip verification platform based on network. - Chuanliang Kang; Pei Yang; Jian Wang 036; Jinmei Lai 001 (ASICON, 2017)

FPGA-based convolution neural network for traffic sign recognition. - Yuchen Yao; Zhiqian Zhang; Zhen Yang; Jian Wang 036; Jinmei Lai 001 (ASICON, 2017)

A SA-based parallel method for FPGA placement. - Chengyu Hu; Peng Lu; Meng Yang 013; Jian Wang 036; Jinmei Lai 001 (IEICE Electron. Express, 2018)

Design of a power efficient self-adaptive LVDS driver. - Hanyang Xu; Jian Wang 036; Jinmei Lai 001 (IEICE Electron. Express, 2018)

A Web-based Waveform Viewer for BR0101 Chip Testing Platform. - Xinyu He; Xie Xie; Jinmei Lai 001; Jian Wang 036 (ASICON, 2019)

An Exponential Dynamic Weighted Fair Queuing Algorithm for Task Scheduling in Chip Verification Platform. - Jiafeng Liu; Zhiyin Lu; Xie Xie; Jian Wang 036; Jinmei Lai 001 (ASICON, 2019)

A Low-delay Configurable Register for FPGA. - Zhi-Yin Lu; Jia-Feng Liu; Yunbing Pang; Zhengjie Li; Yufan Zhang; Jin-Mei Lai 001; Jian Wang 036 (ASICON, 2019)

An FPGA-based log-structure Flash memory system for space exploration. - Huanlin Luo; Yunbo Liu; Hai Ren; Tiantian Zhang; Jian Wang 036; Jinmei Lai 001 (ASICON, 2019)

Design and implementation of Serial ATA pbysical layer on FPGA. - Xie Xie; Qinghua Duan; Jiafeng Liu; Jian Wang 036; Jinmei Lai 001 (ASICON, 2019)

Research on the impact of different benchmark circuits on the representative path in FPGAs. - Jiqing Xu; Zhengjie Li; Yunbing Pang; Jian Wang 036; Gang Qu 001; Jinmei Lai (ASICON, 2019)

Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits. - Zhengjie Li; Yuanlong Xiao; Yufan Zhang; Yunbing Pang; Jian Wang 036; Jinmei Lai 001 (FPGA, 2019)

An Analytical-based Hybrid Algorithm for FPGA Placement. - Chengyu Hu; Qinghua Duan; Liran Hu; Peng Lu; Zhengjie Li; Meng Yang 013; Jian Wang 036; Jinmei Lai 001 (ACM Great Lakes Symposium on VLSI, 2019)

An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization. - Zhengjie Li; Yuanlong Xiao; Yufan Zhang; Yunbing Pang; Chengyu Hu; Jian Wang 036; Jinmei Lai 001 (ACM Great Lakes Symposium on VLSI, 2019)

INTB: A New FPGA Interconnect Model for Architecture Exploration. - Chengyu Hu; Qinghua Duan; Peng Lu; Wei Liu; Jian Wang 036; Jinmei Lai 001 (FPGA, 2020)

FPTLOPT: An Automatic Transistor-Level Optimization Tool for GRM FPGA. - Yufan Zhang; Zhengjie Li; Jian Wang 036; Jinmei Lai 001 (FPGA, 2020)

A Tile-based Interconnect Model for FPGA Architecture Exploration. - Chengyu Hu; Qinghua Duan; Peng Lu; Wei Liu; Jian Wang 036; Jinmei Lai 001 (ACM Great Lakes Symposium on VLSI, 2020)

FABLE-DTS: Hardware-Software Co-Design of a Fast and Stable Data Transmission System for FPGAs. - Jia-Bao Gao; Jian Wang 036; Md Tanvir Arafin; Jin-Mei Lai 001 (SoCC, 2020)

AutoTEA: Automated Transistor-level Efficient and Accurate Optimization for GRM FPGA Design. - Yanze Li; Yufan Zhang; Jiafeng Liu; Jian Wang 036; Jinmei Lai 001; Gang Qu 001 (FCCM, 2021)

An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation Technique. - Wei Xiong; Yanze Li; Changpeng Sun; Huanlin Luo; Jiafeng Liu; Jian Wang 036; Jinmei Lai 001; Gang Qu 001 (ACM Great Lakes Symposium on VLSI, 2022)

AutoTEA: An Automated Transistor-level Efficient and Accurate design tool for FPGA design. - Yanze Li; Yufan Zhang; Jiafeng Liu; Jun Gong; Jian Wang 036; Jinmei Lai 001; Xinxuan Tao; Gang Qu 001 (Integr., 2022)

An Accurate Area Model for FPGA Circuits at Advanced Technologies. - Yanze Li; Zeyu Sun; Jianfan Zhang; Zhichao Wei; Jian Wang 036; Jinmei Lai 001 (ASICON, 2023)

Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm. - Honghong Long; Yu Bai; Yanze Li; Jian Wang 036; Jinmei Lai 001 (ASICON, 2023)

Testing Method for Embedded UltraRAM in Field Programmable Gate Arrays. - Jiaqi Guo; Wei Xiong; Jian Wang 036; Jinmei Lai 001 (ATS, 2024)

A new model for parametrically evaluating the routability of GRM FPGA. - YaoZhang Liu; Wei Xiong; Jian Wang 036; Jin-Mei Lai (IEICE Electron. Express, 2024)

An optimized EEGNet processor for low-power and real-time EEG classification in wearable brain-computer interfaces. - Jiacheng Cao; Wei Xiong; Jie Lu; Peilin Chen; Jian Wang 036; Jinmei Lai 001; Miaoqing Huang (Microelectron. J., 2024)

A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs. - Wei Xiong; Jiacheng Cao; Yaozhang Liu; Jian Wang 036; Jinmei Lai 001; Miaoqing Huang (IEEE Trans. Very Large Scale Integr. Syst., 2024)

An Efficient Traversal Method for FPGA Interconnect Testing Based on Regular Routing. - Wenwei Chen; Lin Ye; XiaoTong Zhao; Tongshu Ding; Jian Wang 036; Jinmei Lai 001 (FPGA, 2025)

Shrink eFPGA tile area by using custom cells and optimizing routing congestion. - Yanze Li; Jian Wang 036; Jinmei Lai 001 (Microelectron. J., 2025)