MSig-BFT: A Witness-Based Consensus Algorithm for Private Blockchains. - Chun-Wei Chen; Jian-Wei Su; Tung-Wei Kuo; Kung Chen (ICPADS, 2018)

Circuit Design Challenges in Computing-in-Memory for AI Edge Devices. - Xin Si; He Qian; Meng-Fan Chang; Cheng-Xin Xue; Jian-Wei Su; Zhixiao Zhang; Sih-Han Li; Shyh-Shyuan Sheu; Heng-Yuan Lee; Ping-Cheng Chen; Huaqiang Wu (ASICON, 2019)

A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors. - Zhixiao Zhang; Jia-Jing Chen; Xin Si; Yung-Ning Tu; Jian-Wei Su; Wei-Hsing Huang; Jing-Hong Wang; Wei-Chen Wei; Yen-Cheng Chiu; Je-Min Hong; Shyh-Shyuan Sheu; Sih-Han Li; et al. (A-SSCC, 2019)

A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training. - Hongwu Jiang; Shanshi Huang; Xiaochen Peng; Jian-Wei Su; Yen-Chi Chou; Wei-Hsing Huang; Ta-Wei Liu; Ruhui Liu; Meng-Fan Chang; Shimeng Yu (DAC, 2020)

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Zhixiao Zhang; Syuan-Hao Sie; et al. (ISSCC, 2020)

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. - Jian-Wei Su; Xin Si; Yen-Chi Chou; Ting-Wei Chang; Wei-Hsing Huang; Yung-Ning Tu; Ruhui Liu; Pei-Jung Lu; Ta-Wei Liu; Jing-Hong Wang; Zhixiao Zhang; Hongwu Jiang; et al. (ISSCC, 2020)

A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors. - Yen-Cheng Chiu; Zhixiao Zhang; Jia-Jing Chen; Xin Si; Ruhui Liu; Yung-Ning Tu; Jian-Wei Su; Wei-Hsing Huang; Jing-Hong Wang; Wei-Chen Wei; Je-Min Hung; Shyh-Shyuan Sheu; et al. (IEEE J. Solid State Circuits, 2020)

A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration. - Chih-Sheng Lin; Fu-Cheng Tsai; Jian-Wei Su; Sih-Han Li; Tian-Sheuan Chang; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang; Chih-I Wu; Tuo-Hung Hou (A-SSCC, 2021)

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips. - Jian-Wei Su; Yen-Chi Chou; Ruhui Liu; Ta-Wei Liu; Pei-Jung Lu; Ping-Chun Wu; Yen-Lin Chung; Li-Yang Hung; Jin-Sheng Ren; Tianlong Pan; Sih-Han Li; Shih-Chieh Chang; et al. (ISSCC, 2021)

A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating. - Jinshan Yue; Xiaoyu Feng; Yifan He 003; Yuxuan Huang; Yipeng Wang 009; Zhe Yuan; Mingtao Zhan; Jiaxin Liu; Jian-Wei Su; Yen-Lin Chung; Ping-Chun Wu; Li-Yang Hung; et al. (ISSCC, 2021)

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Yen-Lin Chung; William Shih; et al. (IEEE J. Solid State Circuits, 2021)

A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. - Ping-Chun Wu; Jian-Wei Su; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Fu-Chun Chang; Yuan Wu 009; Ho-Yu Chen; Chen-Hsun Lin; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; et al. (ISSCC, 2022)

Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips. - Jian-Wei Su; Xin Si; Yen-Chi Chou; Ting-Wei Chang; Wei-Hsing Huang; Yung-Ning Tu; Ruhui Liu; Pei-Jung Lu; Ta-Wei Liu; Jing-Hong Wang; Yen-Lin Chung; Jin-Sheng Ren; et al. (IEEE J. Solid State Circuits, 2022)

A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices. - Ping-Chun Wu; Jian-Wei Su; Li-Yang Hong; Jin-Sheng Ren; Chih-Han Chien; Ho-Yu Chen; Chao-En Ke; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang; et al. (ISSCC, 2023)

A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. - Jian-Wei Su; Yen-Chi Chou; Ruhui Liu; Ta-Wei Liu; Pei-Jung Lu; Ping-Chun Wu; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Tianlong Pan; Chuan-Jia Jhang; Wei-Hsing Huang; et al. (IEEE J. Solid State Circuits, 2023)

Clustering Single-Cell Multi-Omics Data with Graph Contrastive Learning. - Qi Li; Jian-Wei Su; Wen-Hui Wu (ICMLC, 2024)

34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices. - Win-San Khwa; Ping-Chun Wu; Jui-Jen Wu; Jian-Wei Su; Ho-Yu Chen; Zhao-En Ke; Ting-Chien Chiu; Jun-Ming Hsu; Chiao-Yen Cheng; Yu-Chen Chen; Chung-Chuan Lo; Ren-Shuo Liu; et al. (ISSCC, 2024)

Empowering Local Differential Privacy: A 5718 TOPS/W Analog PUF-Based In-Memory Encryption Macro for Dynamic Edge Security. - Chih-Sheng Lin; Bo-Cheng Chiou; Yin-Jia Yang; Jian-Wei Su; Kuo-Hua Tseng; Yun-Ting Ho; Chih-Ming Lai; Sih-Han Li; Tian-Sheuan Chang; Shan-Ming Chang; Shyh-Shyuan Sheu; Wei-Chung Lo; et al. (VLSI Technology and Circuits, 2024)

A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips. - Ping-Chun Wu; Jian-Wei Su; Li-Yang Hong; Jin-Sheng Ren; Chih-Han Chien; Ho-Yu Chen; Chao-En Ke; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang; et al. (IEEE J. Solid State Circuits, 2024)

8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. - Jian-Wei Su; Pei-Jung Lu; Ping-Chun Wu; Yen-Chi Chou; Ta-Wei Liu; Yen-Lin Chung; Li-Yang Hung; Jin-Sheng Ren; Wei-Hsing Huang; Chih-Han Chien; Peng-I Mei; Sih-Han Li; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update. - Jinshan Yue; Yongpan Liu; Xiaoyu Feng; Yifan He 002; Jingyu Wang 004; Zhe Yuan; Mingtao Zhan; Jiaxin Liu; Jian-Wei Su; Yen-Lin Chung; Ping-Chun Wu; Li-Yang Hong; et al. (IEEE J. Solid State Circuits, 2024)

An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips. - Ping-Chun Wu; Jian-Wei Su; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Fu-Chun Chang; Yuan Wu 009; Ho-Yu Chen; Chen-Hsun Lin; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; et al. (IEEE J. Solid State Circuits, 2024)

14.2 A 16nm 216kb, 188.4TOPS/W and 133.5TFLOPS/W Microscaling Multi-Mode Gain-Cell CIM Macro Edge-AI Devices. - Win-San Khwa; Ping-Chun Wu; Jian-Wei Su; Chiao-Yen Cheng; Jun-Ming Hsu; Yu-Chen Chen; Le-Jung Hsieh; Jyun-Cheng Bai; Yu-Sheng Kao; Tsung-Han Lou; Ashwin Sanjay Lele; Jui-Jen Wu; et al. (ISSCC, 2025)

An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips. - Ping-Chun Wu; Win-San Khwa; Jui-Jen Wu; Jian-Wei Su; Chuan-Jia Jhang; Ho-Yu Chen; Zhao-En Ke; Ting-Chien Chiu; Jun-Ming Hsu; Chiao-Yen Cheng; Yu-Chen Chen; Chung-Chuan Lo; et al. (IEEE J. Solid State Circuits, 2025)

3DGauCIM: Accelerating Static/Dynamic 3D Gaussian Splatting via Digital CIM for High Frame Rate Real-Time Edge Rendering. - Wei-Hsing Huang; Cheng-Jhih Shih; Jian-Wei Su; Samuel Wade Wang; Vaidehi Garg; Yuyao Kong; Jen-Chun Tien; Nealson Li; Arijit Raychowdhury; Meng-Fan Chang; Yingyan Lin; Shimeng Yu (CoRR, 2025)