Substrate-engineered GGNMOS for low trigger voltage ESD in 65 nm CMOS process. - Fei Ma; Yan Han; Bo Song; Shurong Dong; Meng Miao; Jianfeng Zheng; Jian Wu 004; Kehan Zhu (Microelectron. Reliab., 2011)

Investigation of ESD protection strategy in high voltage Bipolar-CMOS-DMOS process. - Fei Ma; Yan Han; Shurong Dong; Meng Miao; Jianfeng Zheng; Jian Wu 004; Cheng-gong Han; Kehan Zhu (Microelectron. Reliab., 2012)

A novel gate-suppression technique for ESD protection. - Meng Miao; Shurong Dong; Mingliang Li; Jian Wu 004; Fei Ma; Jianfeng Zheng; Yan Han (Microelectron. Reliab., 2012)

A novel power-clamp assisted complementary MOSFET for robust ESD protection. - Jian Wu 004; Shurong Dong; Mingliang Li; Meng Miao; Fei Ma; Jianfeng Zheng; Yan Han (Microelectron. Reliab., 2012)

300-V class power n-channel LDMOS transistor implemented in 0.18-μm silicon-on-insulator (SOI) technology. - Shuai Zhang 005; Hsiao-Chin Tuan; Xiaojing Wu; Lei Shi; Jian Wu 004 (Microelectron. Reliab., 2016)