Preservation of local linearity by neighborhood subspace scaling for solving the pre-image problem. - Sheng-kai Yang; Jian-Yi Meng; Hai-bin Shen (J. Zhejiang Univ. Sci. C, 2014)

A timing failure tolerance design with in-field simultaneous error detection and correction. - Ziyi Hao; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng (ASICON, 2015)

An energy-efficient microprocessor using multilevel error correction for timing error tolerance. - Sheng Wang 005; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng (ASICON, 2015)

A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correction. - Tao-Tao Zhu; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng (ASICON, 2015)

Value locality based storage compression memory architecture for ECG sensor node. - Chaojun Zhao; Chen Chen 058; Zhijian Chen; Jianyi Meng (Sci. China Inf. Sci., 2016)

EDSU: Error detection and sampling unified flip-flop with ultra-low overhead. - Ziyi Hao; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng; Yong Ding 003; Xiaolang Yan (IEICE Electron. Express, 2016)

Ultralow power processor employing block instruction for ECG applications. - Jing Qiu; Xiaoyan Xiang; Zhijian Chen; Jianyi Meng; Yong Ding 003 (IEICE Electron. Express, 2016)

TBCT: Time-Borrowing and Clock Token based error correction and its application in microprocessor. - Zhenqiang Yong; Xiaoyan Xiang; Jianyi Meng; Chen Chen 058 (IEICE Electron. Express, 2016)

Light-weight one-cycle timing error correction based on hardware software co-design. - Li Zhanhui; Yong Ding 003; Xiaolang Yan; Jianyi Meng; Xiaoyan Xiang (IEICE Electron. Express, 2016)

A light-weight energy-efficient resilient circuit for variation tolerance. - Xiaopei Chen; Sheng Wang 005; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng (ASICON, 2017)

A new error masking flip-flop with one cycle correction penalty. - Zhenqiang Yong; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng (ASICON, 2017)

A lifting wavelet based lossless and lossy ECG compression processor for wireless sensors. - Jiahui Luo; Zhijian Chen; Xiaoyan Xiang; Jianyi Meng (IEICE Electron. Express, 2017)

A dual-mode ECG processor with difference-insensitive QRS detection and lossless compression. - Jiahui Luo; Zhijian Chen; Xiaoyan Xiang; Jianyi Meng; Haibin Shen (IEICE Electron. Express, 2017)

A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs. - Sheng Wang 005; Chen Chen 058; Xiaoyan Xiang; Jianyi Meng (IEICE Electron. Express, 2017)

A granular resampling method based energy-efficient architecture for heartbeat classification in ECG. - Yin Xu 003; Zhijian Chen; Xiaoyan Xiang; Jianyi Meng (IEICE Electron. Express, 2017)

SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor. - Tao-Tao Zhu; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng (IEICE Electron. Express, 2017)

Eliminating Timing Errors Through Collaborative Design to Maximize the Throughput. - Zhan-Hui Li; Tao-Tao Zhu; Zhi-Jian Chen; Jian-Yi Meng; Xiaoyan Xiang; Xiaolang Yan (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Variation-Tolerant Near-Threshold Processor With Instruction-Level Error Correction. - Sheng Wang 005; Chen Chen 058; Xiaoyan Xiang; Jian-Yi Meng (IEEE Trans. Very Large Scale Integr. Syst., 2017)

An Energy-Efficient and Wide-Range Voltage Level Shifter With Dual Current Mirror. - Zhenqiang Yong; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT Processor. - Tao-Tao Zhu; Jian-Yi Meng; Xiaoyan Xiang; Xiaolang Yan (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A low power QRS detection processor with adaptive scaling of processing resolution. - Zhijian Chen; Menghan Jia; Jiahui Luo; Tao-Tao Zhu; Xiaoyan Xiang; Jianyi Meng (IEICE Electron. Express, 2018)

An effectiveness-oriented greedy heuristic for padding short paths in ultra-low supply voltage designs. - Yan He; Jianyi Meng; Zhijian Chen; Xiaoyan Xiang; Chen Chen 058 (IEICE Electron. Express, 2018)

An energy-efficient parallel VLSI architecture for SVM classification. - Yin Xu 003; Zhijian Chen; Xiaoyan Xiang; Jianyi Meng (IEICE Electron. Express, 2018)

A Highly Adaptive Lossless ECG Compression ASIC for Wireless Sensors Based on Hybrid Gomlomb Coding. - Jiahui Luo; Zhijian Chen; Xiaoyan Xiang; Jianyi Meng (IEICE Trans. Inf. Syst., 2018)

ECG-Based Heartbeat Classification Using Two-Level Convolutional Neural Network and RR Interval Difference. - Yande Xiang; Jiahui Luo; Tao-Tao Zhu; Sheng Wang 005; Xiaoyan Xiang; Jianyi Meng (IEICE Trans. Inf. Syst., 2018)

Relative ordering learning in spiking neural network for pattern recognition. - Zhitao Lin; De Ma; Jianyi Meng; Linna Chen (Neurocomputing, 2018)

Low-power perceptron model based ECG processor for premature ventricular contraction detection. - Zhijian Chen; Huanzhang Xu; Jiahui Luo; Tao-Tao Zhu; Jianyi Meng (Microprocess. Microsystems, 2018)

A Cross-layer based mapping for spiking neural network onto network on chip. - Yande Xiang; Jianyi Meng (Int. J. Parallel Emergent Distributed Syst., 2018)

An Energy-Efficient ECG Processor With Weak-Strong Hybrid Classifier for Arrhythmia Detection. - Zhijian Chen; Jiahui Luo; Kaiwen Lin; Jiaquan Wu; Tao-Tao Zhu; Xiaoyan Xiang; Jianyi Meng (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

SCSE: Boosting Symbolic Execution via State Concretization. - Huibin Wang; Chunqiang Li; Jianyi Meng; Xiaoyan Xiang (IEICE Trans. Inf. Syst., 2019)

A Granular Resampling Method and Adaptive Speculative Mechanism-Based Energy-Efficient Architecture for Multiclass Heartbeat Classification. - Yin Xu 003; Zhijian Chen; Feiteng Li; Jianyi Meng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Xuantie-910: Innovating Cloud and Edge Computing by RISC-V. - Chen Chen 058; Xiaoyan Xiang; Chang Liu 021; Yunhai Shang; Ren Guo; Dongqi Liu 003; Yimin Lu; Ziyi Hao; Jiahui Luo; Zhijian Chen; Chunqiang Li; Yu Pu; et al. (Hot Chips Symposium, 2020)

Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product. - Chen Chen 058; Xiaoyan Xiang; Chang Liu 021; Yunhai Shang; Ren Guo; Dongqi Liu 003; Yimin Lu; Ziyi Hao; Jiahui Luo; Zhijian Chen; Chunqiang Li; Yu Pu; et al. (ISCA, 2020)

Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. - Zhaoyang Du; Yijin Guan; Tianchan Guan; Dimin Niu; Nianxiong Tan; Xiaopeng Yu 002; Hongzhong Zheng; Jianyi Meng; Xiaolang Yan; Yuan Xie 001 (ICPADS, 2022)

Enhancing RISC-V Vector Extension for Efficient Application of Post-Quantum Cryptography. - Yifan Zhao 007; Honglin Kuang; Yi Sun; Zhen Yang; Chen Chen 058; Jianyi Meng; Jun Han 003 (ASAP, 2023)