Robust design with virtual tests of mixed-signal circuits in VHDL-AMS. - Jian-Yi Wu; Steven B. Bibyk (ISCAS (5), 2002)

Multi-Bit Sigma Delta ADC with Reduced Feedback Levels, Extended Dynamic Range and Increased Tolerance for Analog Imperfections. - Jian-Yi Wu; Raj Subramoniam; Zhenyong Zhang; Ali Djabbari; Peter Holloway; Franco Maloberti; Masood Yousefi; Mehmat Aslan; Hua Hong; Ahmad Bahai (CICC, 2007)

A 107.4 dB SNR Multi-Bit Sigma Delta ADC With 1-PPM THD at -0.12 dB From Full Scale Input. - Jian-Yi Wu; Zhenyong Zhang; Raj Subramoniam; Franco Maloberti (IEEE J. Solid State Circuits, 2009)

Design and implementation of a bluetooth air finger mouse. - Hui-Kai Su; Hua-Yi Wu; Jian-Yi Wu; Ting-Wei Man; Chien-Min Wu; Chi-Chia Sun (ICCE-TW, 2014)