Jian Zhang

Affiliations:
  • EPFL, Integrated Systems Laboratory, Lausanne, Switzerland


According to our database1, Jian Zhang authored at least 8 papers between 2012 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

Online presence:

On csauthors.net:

Bibliography

2016
A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.
ACM J. Emerg. Technol. Comput. Syst., 2016

2015
A surface potential and current model for polarity-controllable silicon nanowire FETs.
Proceedings of the 45th European Solid State Device Research Conference, 2015

2014
Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Advanced system on a chip design based on controllable-polarity FETs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012


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