Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors. - Shashikanth Bobba; Pierre-Emmanuel Gaillardon; Jian Zhang 067; Michele De Marchi; Davide Sacchetto; Yusuf Leblebici; Giovanni De Micheli (NANOARCH, 2012)

Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs. - Jian Zhang 067; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ISCAS, 2013)

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors. - Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Jian Zhang 067; Giovanni De Micheli (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Advanced system on a chip design based on controllable-polarity FETs. - Pierre-Emmanuel Gaillardon; Luca Gaetano Amarù; Jian Zhang 067; Giovanni De Micheli (DATE, 2014)

TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs. - Xifan Tang; Jian Zhang 067; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ISCAS, 2014)

Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs. - Jian Zhang 067; Xifan Tang; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A surface potential and current model for polarity-controllable silicon nanowire FETs. - Jian Zhang 067; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ESSDERC, 2015)

A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors. - Hassan Ghasemzadeh Mohammadi; Pierre-Emmanuel Gaillardon; Jian Zhang 067; Giovanni De Micheli; Ernesto Sánchez 001; Matteo Sonza Reorda (ACM J. Emerg. Technol. Comput. Syst., 2016)