An efficient optimization method of RF passive components using RBF model. - Sen Yin; Wenfei Hu; Wenyuan Zhang 001; Ruitao Wang; Jian Zhang 085; Yan Wang 023 (ASICON, 2021)

Large-scale Integrated Circuits Simulation Based on CNT-FET Model. - Zhikai Wang; Wenfei Hu; Ziyu Gu; Wenyuan Zhang 001; Sen Yin; Ruitao Wang; Jian Zhang 085; Yan Wang 023 (ICICDT, 2021)

An Efficient Kriging-based Constrained Multi-objective Evolutionary Algorithm for Analog Circuit Synthesis via Self-adaptive Incremental Learning. - Sen Yin; Wenfei Hu; Wenyuan Zhang 001; Ruitao Wang; Jian Zhang 085; Yan Wang 023 (ASP-DAC, 2022)

Building Post-layout Performance Model of Analog/RF Circuits by Fine-tuning Technique. - Zhikai Wang; Wenfei Hu; Jingbo Zhou; Wenyuan Zhang 001; Ruitao Wang; Jian Zhang 085; Dejing Dou; Zuochang Ye; Yan Wang 023 (ISQED, 2022)

A 1V 32.1 dBm 92-to-102GHz Power Amplifier with a Scalable 128-to-1 Power Combiner Achieving 15% Peak PAE in a 65nm Bulk CMOS Process. - Wei Zhu 017; Jiawen Wang; Ruitao Wang; Jian Zhang 085; Chenguang Li; Sen Yin; Yan Wang 023 (ISSCC, 2022)

An Ultra-compact Bidirectional T/R Folded 25.8-39.2GHz Phased-Array Transceiver Front-End with Embedded TX Power Detection/Self-calibration Path Supporting 64-/256-/512-QAM at 28-/39-GHz band for 5G in 65nm CMOS Technology. - Wei Zhu 017; Ruitao Wang; Jian Zhang 085; Jiawen Wang; Chenguang Li; Yan Wang 023 (VLSI Technology and Circuits, 2022)

A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP. - Wei Zhu 017; Jian Zhang 085; Jiawen Wang; Ruitao Wang; Chenguang Li; Kai Wang; Yan Wang 023 (VLSI Technology and Circuits, 2022)

Asynchronous Parallel Expected Improvement Matrix-Based Constrained Multi-Objective Optimization for Analog Circuit Sizing. - Sen Yin; Ruitao Wang; Jian Zhang 085; Yan Wang 023 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Ka-Band Mutual Coupling Resilient Balanced PA with Magnetic Coupling Self-Cancelling Inductor Achieving 21.2dBm OP1dBand 27.6% PAE1dB. - Jian Zhang 085; Wei Zhu 017; Dawei Wang; Xiangjie Yi; Ruitao Wang; Yan Wang 023 (A-SSCC, 2023)

A Hybrid Integrated W-Band 4-Element Phased-Array Transceiver Front-End Achieving 21.6% Full TX Peak PAE at 14.8dBm Output Power and <1°/dB Phase/Gain Resolution in 65-nm CMOS Technology. - Wei Zhu 017; Jian Zhang 085; Jiazhi Ying; Xiangjie Yi; Yan Wang 023; Houjun Sun (A-SSCC, 2023)

Fast Surrogate-Assisted Constrained Multiobjective Optimization for Analog Circuit Sizing via Self-Adaptive Incremental Learning. - Sen Yin; Ruitao Wang; Jian Zhang 085; Xiaosen Liu; Yan Wang 023 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

32.8 A 27.8-to-38.7GHz Load-Modulated Balanced Power Amplifier with Scalable 7-to-1 Load-Modulated Power-Combine Network Achieving 27.2dBm Output Power and 28.8%/23.2%/16.3%/11.9% Peak/6/9/12dB Back-Off Efficiency. - Wei Zhu 017; Jiazhi Ying; Long Chen; Jian Zhang 085; Guanshen Lv; Xiangjie Yi; Zhiqiang Zhao; Zunxiang Wang; Yan Wang 023; Wenhua Chen; Houjun Sun (ISSCC, 2024)

Automatic Design for W-Band Front-End System via Bottom-Up Sizing and Layout Generation. - Sen Yin; Ruitao Wang; Jian Zhang 085; Xiaosen Liu; Yan Wang 023 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A Broadband Bidirectional Four-Element Four-Beam Beamformer With Compact Floorplan in a 65nm CMOS Technology. - Jian Zhang 085; Ming Zhai; Yichen Liu; Xiangjie Yi; Dawei Wang; Wei Zhu 017; Yan Wang 023 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)