Low-Cost DNN Hardware Accelerator for Wearable, High-Quality Cardiac Arrythmia Detection. - Johnson Loh; Jianan Wen; Tobias Gemmeke (ASAP, 2020)

Behavioral Model of Dot-Product Engine Implemented with 1T1R Memristor Crossbar Including Assessment. - Jianan Wen; Markus Ulbricht 002; Eduardo Pérez; Xin Fan 003; Milos Krstic (DDECS, 2021)

Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages. - Jianan Wen; Andrea Baroni; Eduardo Pérez; Markus Ulbricht 002; Christian Wenger; Milos Krstic (DFT, 2022)

LUT-based RRAM Model for Neural Accelerator Circuit Simulation. - Max Uhlmann; Tommaso Rizzi; Jianan Wen; Emilio Pérez-Bosch Quesada; Bakr Al Beattie; Karlheinz Ochs; Eduardo Pérez; Philip Ostrovskyy; Corrado Carta; Christian Wenger; Gerhard Kahmen (NANOARCH, 2023)

Prototyping Reconfigurable RRAM-Based AI Accelerators Using the RISC-V Ecosystem and Digital Twins. - Markus Fritscher; Alessandro Veronesi; Andrea Baroni; Jianan Wen; Thorsten Spätling; Mamathamba Kalishettyhalli Mahadevaiah; Norbert Herfurth; Eduardo Pérez; Markus Ulbricht 002; Marc Reichenbach; Amelie Hagelauer; Milos Krstic (ISC Workshops, 2023)

Towards Reliable and Energy-Efficient RRAM Based Discrete Fourier Transform Accelerator. - Jianan Wen; Andrea Baroni; Eduardo Pérez; Max Uhlmann; Markus Fritscher; Karthik KrishneGowda; Markus Ulbricht 002; Christian Wenger; Milos Krstic (DATE, 2024)

Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment. - Jianan Wen; Fabian Luis Vargas 001; Fukun Zhu; Daniel Reiser; Andrea Baroni; Markus Fritscher; Eduardo Pérez; Marc Reichenbach; Christian Wenger; Milos Krstic (LATS, 2024)

HyRPF: Hybrid RRAM Prototyping on FPGA. - Daniel Reiser; Johannes Knödtel; Liliia Almeeva; Jianan Wen; Andrea Baroni; Milos Krstic; Marc Reichenbach (SAMOS, 2024)

ReDiM: An Efficient Strategy for Read Disturb Mitigation in RRAM-Based Accelerators. - Jianan Wen; Andrea Baroni; Alberto Mistroni; Eduardo Pérez; Cristian Zambelli; Christian Wenger; Milos Krstic; Letícia Maria Veiras Bolzani (IOLTS, 2025)

RISC-V CPU Design Using RRAM-CMOS Standard Cells. - Markus Fritscher; Max Uhlmann; Philip Ostrovskyy; Daniel Reiser; Junchao Chen 001; Jianan Wen; Carsten Schulze; Gerhard Kahmen; Dietmar Fey; Marc Reichenbach; Milos Krstic; Christian Wenger (IEEE Trans. Very Large Scale Integr. Syst., 2025)