Module placement with boundary constraints using the sequence-pair representation. - Jianbang Lai; Ming-Shiun Lin; Ting-Chi Wang; Li-C. Wang (ASP-DAC, 2001)

Power minization in LUT-based FPGA technology mapping. - Zhi-Hong Wang; En-Cheng Liu; Jianbang Lai; Ting-Chi Wang (ASP-DAC, 2001)

Module placement with pre-placed modules using the B*-tree representation. - Yi-He Jiang; Jianbang Lai; Ting-Chi Wang (ISCAS (5), 2001)

Slicing floorplan design with boundary-constrained modules. - En-Cheng Liu; Ming-Shiun Lin; Jianbang Lai; Ting-Chi Wang (ISPD, 2001)