A 5-13.5 Gb/s Multistandard Receiver With High Jitter Tolerance Digital CDR in 40-nm CMOS Process. - Zhou Shu; Shalin Huang; Zhipeng Li; Peng Yin 004; Jiandong Zang; Dongbing Fu; Fang Tang; Amine Bermak (IEEE Trans. Circuits Syst., 2020)

A Low-Area and Low-Power Comma Detection and Word Alignment Circuits for JESD204B/C Controller. - Peng Yin 004; Zhou Shu; Yingjun Xia; Tianmei Shen; Xiao Guan; Xiaoqin Wang; Umar Mohammad; Jiandong Zang; Dongbing Fu; Xiaoping Zeng; Fang Tang; Amine Bermak (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

An 8 GHz Semi-Digital DLL for CDR in High Speed SerDes Receivers. - Yi Ding; Jiandong Zang; Jun Liu (CNIOT, 2024)