A new asynchronous delay-insensitive link based on a 1-of-4 LETS code. - Can Wang; Qin Wang 009; Jianfei Jiang 001 (ASICON, 2011)

An efficient 90nm technology-node GHz transceiver of on-chip global interconnect. - Zaixiao Zheng; Zhigang Mao; Jianfei Jiang 001 (ASICON, 2011)

A novel low power 64-kb SRAM using bit-lines charge-recycling and non-uniform cell scheme. - Xu Wang; Jianfei Jiang 001; Zhi-Gang Mao; Bingjing Ge; Xinglong Zhao (ICECS, 2011)

A clock-less transceiver for global interconnect. - Jianfei Jiang 001; Xu Wang; Wei-Guang Sheng; Wei-Feng He; Zhi-Gang Mao (VLSI-SoC, 2011)

Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm. - Weiguang Sheng; Weifeng He; Jianfei Jiang 001; Zhigang Mao (IPDPS Workshops, 2012)

A pre-emphasis circuit design for high speed on-chip global interconnect. - Jianfei Jiang 001; Wei-Guang Sheng; Zhi-Gang Mao; Wei-Feng He (ISCAS, 2012)

Design of a high voltage stimulator chip for a stroke rehabilitation system. - Lei Zeng; Xin Yi; Sheng Lu; Yuan Lou; Jianfei Jiang 001; Hongen Qu; Ning Lan; Guoxing Wang (EMBC, 2013)

Modeling and analysis of signal transmission with Through Silicon Via (TSV) noise coupling. - Zhenyang Chen; Qin Wang 009; Jing Xie 010; Jin Tian; Jianfei Jiang 001; Yufei Li; Wen Yin (ISCAS, 2013)

A crosstalk avoidance scheme based on re-layout of signal TSV. - Jiayi Hu; Qin Wang 009; Jianfei Jiang 001; Jing Xie 010; Zhigang Mao (ASICON, 2015)

Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs. - Naifeng Jing; Jiacheng Zhou; Jianfei Jiang 001; Xin Chen; Weifeng He; Zhigang Mao (ICCAD, 2015)

A contactless testing methodology for pre-bond interposer. - Jianfei Jiang 001; Weiguang Sheng; Qin Wang 009; Zhigang Mao (MWSCAS, 2015)

Design optimization for capacitive-resistively driven on-chip global interconnect. - Jianfei Jiang 001; Weifeng He; Jizeng Wei; Qin Wang 009; Zhigang Mao (IEICE Electron. Express, 2015)

Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing. - Zhiting Yan; Guanghui He; Yifan Ren; Weifeng He; Jianfei Jiang 001; Zhigang Mao (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects. - Jianfei Jiang 001; Zhigang Mao; Weiguang Sheng; Qin Wang 009; Weifeng He (J. Circuits Syst. Comput., 2016)

Parallel SER analysis for combinational and sequential standard cell circuits. - Weiguang Sheng; Jianfei Jiang 001; Zhigang Mao (Microelectron. J., 2016)

A metastability-based true random number generator on FPGA. - Chaoyang Li 008; Qin Wang 009; Jianfei Jiang 001; Nin Guan (ASICON, 2017)

An on-chip circuit for timing measurement of SRAM IP. - Xianjie Long; Qin Wang 009; Jianfei Jiang 001; Nin Guan (ASICON, 2017)

A 0.2V 2.3pJ/Cycle 28dB output SNR hybrid Markov random field probabilistic-based circuit for noise immunity and energy efficiency. - Xuwei Jin; Wei Jin 004; Hao Zhang 151; Jianfei Jiang 001; Weifeng He (ISCAS, 2017)

A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS. - Wei Jin 004; Weifeng He; Jianfei Jiang 001; Haichao Huang; Xuejun Zhao; Yanan Sun 003; Xin Chen; Naifeng Jing (Integr., 2017)

Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC. - Qin Wang 009; Zhenyang Chen; Jianfei Jiang 001; Zheng Guo 001; Zhigang Mao (Integr., 2017)

Deploying and Optimizing Convolutional Neural Networks on Heterogeneous Architecture. - Junning Jiang; Liang Cai; Feng Dong; Kehua Yu; Ke Chen; Wei Qu; Jianfei Jiang 001 (ASICON, 2019)

A New Approximate Multiplier Design for Digital Signal Processing. - Yue Zhao; Tong Li; Feng Dong; Qin Wang 009; Weifeng He; Jianfei Jiang 001 (ASICON, 2019)

A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs. - Sijie Zheng; Hongjun You; Guanghui He; Qin Wang 009; Tao Si; Jianfei Jiang 001; Jing Jin 005; Naifeng Jing (ISCAS, 2019)

A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations. - Taozhong Li; Qin Wang 009; Yongxin Zhu 001; Jianfei Jiang 001; Guanghui He; Jing Jin 005; Zhigang Mao; Naifeng Jing (ACM Trans. Design Autom. Electr. Syst., 2019)

A New Cellular-Based Redundant TSV Structure for Clustered Faults. - Qin Wang 009; Zechen Liu; Jianfei Jiang 001; Naifeng Jing; Weiguang Sheng (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Frequency Attention Network: Blind Noise Removal for Real Images. - Hongcheng Mo; Jianfei Jiang 001; Qin Wang 009; Dong Yin; Pengyu Dong; Jingjun Tian (ACCV (2), 2020)

Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array. - Tu Hong; Ning Guan; Chen Yin; Qin Wang 009; Jianfei Jiang 001; Jing Jin 005; Guanghui He; Naifeng Jing (ISCAS, 2020)

Priority Branches for Ship Detection in Optical Remote Sensing Images. - Yijia Zhang; Weiguang Sheng; Jianfei Jiang 001; Naifeng Jing; Qin Wang 009; Zhigang Mao (Remote. Sens., 2020)

An Efficient Massive MIMO Detector Based on Second-Order Richardson Iteration: From Algorithm to Flexible Architecture. - Jiaming Tu; Mengdan Lou; Jianfei Jiang 001; Dewu Shu; Guanghui He (IEEE Trans. Circuits Syst., 2020)

A CPU-FPGA Based Heterogeneous Accelerator for RepVGG. - Yiliang Guo; Mingjun Jiang; Feng Dong; Kehua Yu; Ke Chen; Wei Qu; Jianfei Jiang 001 (ASICON, 2021)

A Mapping Method for Reconfigurable Array based on Decoupled DataFlow. - Zihan Zhang; Jianfei Jiang 001; Weiguang Sheng; Qin Wang 009; Zhigang Mao; Naifeng Jing (BigDataSecurity, 2021)

Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture. - Yuge Chen; Zhongyuan Zhao 004; Jianfei Jiang 001; Guanghui He; Zhigang Mao; Weiguang Sheng (DATE, 2021)

Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. - Chen Yin; Qin Wang 009; Jianfei Jiang 001; Weiguang Sheng; Guanghui He; Zhigang Mao; Naifeng Jing (DATE, 2021)

Fast FPGA-Based Emulation for ReRAM-Enabled Deep Neural Network Accelerator. - Yongquan Shi; Yongshuai Sun; Jianfei Jiang 001; Guanghui He; Qin Wang 009; Naifeng Jing (ISCAS, 2021)

Boosting ReRAM-based DNN by Row Activation Oversubscription. - Mengyu Guo; Zihan Zhang; Jianfei Jiang 001; Qin Wang 009; Naifeng Jing (ASP-DAC, 2022)

A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images. - Guochao Deng; Qin Wang 009; Jianfei Jiang 001; Qirun Hong; Naifeng Jing; Weiguang Sheng; Zhigang Mao (IEEE Geosci. Remote. Sens. Lett., 2022)

A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator. - Zihan Zhang; Jianfei Jiang 001; Yongxin Zhu 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A CPU-FPGA Heterogeneous Acceleration System for Scene Text Detection Network. - Jianfei Jiang 001; Mingjun Jiang; Jiayu Zhang; Feng Dong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator. - Taozhong Li; Naifeng Jing; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Yiran Chen 001 (ACM Trans. Design Autom. Electr. Syst., 2022)

An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs. - Shengzhao Li; Qin Wang 009; Jianfei Jiang 001; Weiguang Sheng; Naifeng Jing; Zhigang Mao (IEEE Trans. Very Large Scale Integr. Syst., 2022)

ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse ReRAM Accelerator. - Zhuo Chen; Zihan Zhang; Jianfei Jiang 001; Weiguang Sheng; Qin Wang 009; Naifeng Jing (ASICON, 2023)

High-Performance Genomic Analysis Heterogeneous System Using OpenCL. - Jianing Gao; Lingyi Liu; Qin Wang 009; Naifeng Jing; Jianfei Jiang 001 (ASICON, 2023)

An NoC-based CNN Accelerator for Edge Computing. - Jianing Gao; Qiming Shao; Fangyu Deng; Qin Wang 009; Naifeng Jing; Jianfei Jiang 001 (ASICON, 2023)

MUG5: Modeling of Universal Chiplet Interconnect Express (UCIe) Standard Based on gem5. - Xiaoyan Li; Zizheng Dong; Shuaipeng Li; Sai Gao; Jianfei Jiang 001; Guanghui He; Zhigang Mao (ASICON, 2023)

An Efficient near-Bank Processing Architecture for Personalized Recommendation System. - Yuqing Yang; Weidong Yang; Qin Wang 009; Naifeng Jing; Jianfei Jiang 001; Zhigang Mao; Weiguang Sheng (ASP-DAC, 2023)

Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture. - Pengyu Liu 004; Zihan Zhang; Chen Yin; Liyan Chen; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (FPL, 2023)

ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors. - Shuya Ji; Weidong Yang; Jianfei Jiang 001; Naifeng Jing; Weiguang Sheng; Ang Li; Qin Wang 009 (ICCD, 2023)

A Hierarchical Communication Algorithm for Distributed Deep Learning Training. - Jiayu Zhang; Shaojun Cheng; Feng Dong; Ke Chen; Yong Qiao; Zhigang Mao; Jianfei Jiang 001 (MWSCAS, 2023)

RTMDet-R2: An Improved Real-Time Rotated Object Detector. - Haifeng Xiang; Naifeng Jing; Jianfei Jiang 001; Hongbo Guo; Weiguang Sheng; Zhigang Mao; Qin Wang 009 (PRCV (12), 2023)

Exploiting bit sparsity in both activation and weight in neural networks accelerators. - Naifeng Jing; Zihan Zhang; Yongshuai Sun; Pengyu Liu 004; Liyan Chen; Qin Wang 009; Jianfei Jiang 001 (Integr., 2023)

A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration. - Chen Yin; Naifeng Jing; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture. - Liyan Chen; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (ASPDAC, 2024)

SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration. - Chen Yin; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (ASPDAC, 2024)

Enabling Multiple Tensor-wise Operator Fusion for Transformer Models on Spatial Accelerators. - Lei Xu; Zhiwen Mo; Qin Wang 009; Jianfei Jiang 001; Naifeng Jing (DAC, 2024)

Compact Powers-of-Two: An Efficient Non-Uniform Quantization for Deep Neural Networks. - Xinkuang Geng; Siting Liu 001; Jianfei Jiang 001; Kai Jiang; Honglan Jiang (DATE, 2024)

VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks. - Duo Yu; Ang Li; Naifeng Jing; Jianfei Jiang 001; Weiguang Sheng; Qin Wang 009 (ACM Great Lakes Symposium on VLSI, 2024)

A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction. - Lin Xie; Zizheng Dong; Jialei Sun; Sai Gao; Shuaipeng Li; Naifeng Jing; Qin Wang 009; Jianfei Jiang 001 (ISCAS, 2024)

A novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance. - Kunyue Li; Zhengji Zhao; Qixuan Cai; Qin Wang 009; Naifeng Jing; Zhigang Mao; Jianfei Jiang 001 (Expert Syst. Appl., 2024)

3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator. - Zihan Zhang; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With Delta Updating. - Chen Yin; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture. - Weidong Yang; Yuqing Yang; Shuya Ji; Jianfei Jiang 001; Naifeng Jing; Qin Wang 009; Zhigang Mao; Weiguang Sheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A Comprehensive Dataflow-Mapping Optimization for Fully Pipelined Execution in Spatial Programmable Architecture. - Pengyu Liu 004; Ang Li; Liyan Chen; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

MDNMP: Metapath-Driven Software-Hardware Co-Design for HGNN Acceleration with Near-Memory Processing. - Liyan Chen; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (ASP-DAC, 2025)

HEILP: An ILP-Based Scale Management Method for Homomorphic Encryption Compiler. - Weidong Yang; Shuya Ji; Jianfei Jiang 001; Naifeng Jing; Qin Wang 009; Zhigang Mao; Weiguang Sheng (DATE, 2025)

AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory Processing. - Liyan Chen; Dongxu Lyu; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (HPCA, 2025)

A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip. - Zizheng Dong; Shuaipeng Li; Weijia Zhu; Ang Li; Qin Wang 009; Naifeng Jing; Weiguang Sheng; Jianfei Jiang 001; Zhigang Mao (IEEE Trans. Very Large Scale Integr. Syst., 2025)

VEDA: Efficient LLM Generation Through Voting-based KV Cache Eviction and Dataflow-flexible Accelerator. - Zhican Wang; Hongxiang Fan; Haroon Waris; Gang Wang; Zhenyu Li; Jianfei Jiang 001; Yanan Sun 003; Guanghui He (CoRR, 2025)

Bridge-NDP: Efficient Communication-Computation Overlap in Near Data Processing System. - Liyan Chen; Pengyu Liu 004; Dongxu Lyu; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

MACS: A Multidomain Collaborative Adaptive Clock Scheme for Large-Scale Reconfigurable Dataflow Accelerators. - Shuya Ji; Weidong Yang; Jianfei Jiang 001; Naifeng Jing; Honglan Jiang; Zhigang Mao; Qin Wang 009 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

An Energy-Efficient CPU-FPGA Heterogeneous Acceleration System for Third-Generation Genomic Sequencing Based on Minimap2. - Jialei Sun; Lingyi Liu; Kunyue Li; Shuaipeng Li; Sai Gao; Zizheng Dong; Jianfei Jiang 001; Fangzhen Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

IPDR: An Inter-Chiplet Priority-Driven Deadlock Resolution for 2-D/2.5-D Multichiplet Systems. - Jinming Zhang; Zhihong Chen; Yaoyao Ye; Hao Chen; Xiao Han; Jianfei Jiang 001; Weiguang Sheng; Ningyi Xu; Yong Lian 001; Guanghui He (IEEE Trans. Very Large Scale Integr. Syst., 2025)