An Efficient Verification Method for Microprocessors Based on the Virtual Machine. - Jianfeng An; Xiaoya Fan; Shengbing Zhang; Danghui Wang (ICESS, 2004)

Microprocessor Based Self Schedule and Parallel BIST for System-On-a-Chip. - Danghui Wang; Xiaoya Fan; Deyuan Gao; Shengbing Zhang; Jianfeng An (ICESS, 2005)

VMSIM: Virtual Machine Based a Full System Simulation Platform for Microprocessors' Functional Verification. - Jianfeng An; Xiaoya Fan; Shengbing Zhang; Danghui Wang; Yi Wang 016 (ITNG, 2006)

Global Prefetcher Aggressiveness Control for Chip-Multiprocessor. - Limin Han; Deyuan Gao; Xiaoya Fan; Liwen Shi; Jianfeng An (CIS, 2011)

Modeling and Performance Analysis of Network on Chip Based on Improved Asymmetric Multi-channel Router. - Xianglong Ren; Deyuan Gao; Xiaoya Fan; Jianfeng An; Tao Yao (CIT, 2012)

A Novel Architecture to Identify the Microprocessor Chips by Implanting Timing-Fault Execution Unit. - Xiaoping Huang; Jianfeng An (CSE, 2013)

Speed up an x86 SAME simulator using synthesizable SystemC timing models. - Jianfeng An; Yi Wang 016 (MWSCAS, 2016)

DRAM write-only-cache for improving lifetime of phase change memory. - Chao Chen; Jianfeng An (MWSCAS, 2016)

Unified data authenticated encryption for vehicular communication. - Yi Wang 016; Jianfeng An; Yajun Ha (MWSCAS, 2016)

Shift-Optimized Energy-Efficient Racetrack-Based Main Memory. - Danghui Wang; Lang Ma; Meng Zhang; Jianfeng An; Hai Helen Li; Yiran Chen 001 (J. Circuits Syst. Comput., 2018)

A Highly Efficient Heterogeneous Processor for SAR Imaging. - Shiyu Wang; Shengbing Zhang; Xiaoping Huang; Jianfeng An; Libo Chang (Sensors, 2019)

FIG-QEMU: A Fault Inject Platform Supporting Full System Simulation. - Jianfeng An; Hongjun You; Fengqing Xie; Yuanlin Yang 002; Jinhua Sun (DSA, 2020)

Fault Tolerant XY-YX Routing Algorithm Supporting Backtracking Strategy for NoC. - Jianfeng An; Hongjun You; Jinhua Sun; Jiawei Cao (ISPA/BDCloud/SocialCom/SustainCom, 2021)

ERDSE: efficient reinforcement learning based design space exploration method for CNN accelerator on resource limited platform. - Kaijie Feng; Xiaoya Fan; Jianfeng An; Xiping Wang; Kaiyue Di; Jiangfei Li; Minghao Lu; Chuxi Li (Graph. Vis. Comput., 2021)

A Linear NAS Service of ConvNets for Fast Deployment in the Edge of 5G Networks. - Jihe Wang; Jiaxiang Zhao; Jianfeng An; Danghui Wang; Meikang Qiu (IEEE Netw., 2021)

An Automatic-Addressing Architecture With Fully Serialized Access in Racetrack Memory for Energy-Efficient CNNs. - Jihe Wang; Jun Liu; Danghui Wang; Jianfeng An; Xiaoya Fan (IEEE Trans. Computers, 2022)

CSDSE: Apply Cooperative Search to Solve the Exploration-Exploitation Dilemma of Design Space Exploration. - Kaijie Feng; Xiaoya Fan; Jianfeng An; Haoyang Wang 014; Chuxi Li (ICA3PP (4), 2023)

A gated multi-hierarchical feature fusion network for recognizing steel plate surface defects. - Huanjie Tao; Minghao Lu; Zhenwu Hu; Jianfeng An (Multim. Syst., 2023)

An Adaptive Interference Removal Framework for Video Person Re-Identification. - Huanjie Tao; Qianyue Duan; Jianfeng An (IEEE Trans. Circuits Syst. Video Technol., 2023)

An improved interaction-and-aggregation network for person re-identification. - Huanjie Tao; Wenjie Bao; Qianyue Duan; Zhenwu Hu; Jianfeng An; Chao Xie (Multim. Tools Appl., 2023)

ACDSE: A Design Space Exploration Method for CNN Accelerator based on Adaptive Compression Mechanism. - Kaijie Feng; Xiaoya Fan; Jianfeng An; Chuxi Li; Kaiyue Di; Jiangfei Li (ACM Trans. Embed. Comput. Syst., 2023)

LCDSE: Enable Efficient Design Space Exploration for DCNN Accelerator Based on Layer Clustering. - Kaijie Feng; Xiaoya Fan; Jianfeng An (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

PRDSE: A Prior-Driven Design Space Exploration Method. - Junda Zhu 007; Xiaoya Fan; Jianfeng An; Kaijie Feng (ASAP, 2025)

CSDSE: An efficient design space exploration framework for deep neural network accelerator based on cooperative search. - Kaijie Feng; Xiaoya Fan; Jianfeng An; Haoyang Wang 014; Chuxi Li (Neurocomputing, 2025)