A layout dependent full-chip copper electroplating topography model. - Jianfeng Luo 001; Qing Su; Charles C. Chiang; Jamil Kawa (ICCAD, 2005)

An IC manufacturing yield model considering intra-die variations. - Jianfeng Luo 001; Subarna Sinha; Qing Su; Jamil Kawa; Charles C. Chiang (DAC, 2006)

Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process. - Subarna Sinha; Jianfeng Luo 001; Charles C. Chiang (ASP-DAC, 2007)

Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. - Debjit Sinha; Jianfeng Luo 001; Subramanian Rajagopalan; Shabbir H. Batterywala; Narendra V. Shenoy; Hai Zhou 001 (VLSI Design, 2007)