A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only). - Jianfeng Zhu 001; Dong Wu; Yaru Yan; Xiao Yu; Hu He 001; Liyang Pan (FPGA, 2011)

A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect. - Jianfeng Zhu 001; Hu He 001; Dong Wu; Liyang Pan (J. Electron. Test., 2011)

Erratum to: A Cost-Efficient Self-Configurable BIST Technique for Testing Multiplexer-Based FPGA Interconnect. - Jianfeng Zhu 001; Hu He 001; Dong Wu; Liyang Pan (J. Electron. Test., 2011)

Low-Power Reconfigurable Processor Utilizing Variable Dual VDD. - Jianfeng Zhu 001; Leibo Liu; Shouyi Yin; Shaojun Wei (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA. - Jianfeng Zhu 001; Liyang Pan; Yaru Yan; Dong Wu; Hu He 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Acceleration of control flows on reconfigurable architecture with a composite method. - Junbin Wang; Leibo Liu; Jianfeng Zhu 001; Shouyi Yin; Shaojun Wei (DAC, 2015)

A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only). - Junbin Wang; Leibo Liu; Jianfeng Zhu 001; Shouyi Yin; Shaojun Wei (FPGA, 2015)

A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels. - Jianfeng Zhu 001; Leibo Liu; Shouyi Yin; Xiao Yang; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2015)

TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions. - Leibo Liu; Junbin Wang; Jianfeng Zhu 001; Chenchen Deng; Shouyi Yin; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2016)

A General Pattern-Based Dynamic Compilation Framework for Coarse-Grained Reconfigurable Architectures. - Xingchen Man; Leibo Liu; Jianfeng Zhu 001; Shaojun Wei (DAC, 2019)

Jintide®: A Hardware Security Enhanced Server CPU with Xeon® Cores under Runtime Surveillance by an In-Package Dynamically Reconfigurable Processor. - Leibo Liu; Ao Luo; Guanhua Li; Jianfeng Zhu 001; Yong Wang; Gang Shan; Jianfeng Pan; Shouyi Yin; Shaojun Wei (Hot Chips Symposium, 2019)

A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications. - Leibo Liu; Jianfeng Zhu 001; Zhaoshi Li; Yanan Lu; Yangdong Deng; Jie Han 001; Shouyi Yin; Shaojun Wei (ACM Comput. Surv., 2020)

Pattern-Based Dynamic Compilation System for CGRAs With Online Configuration Transformation. - Leibo Liu; Xingchen Man; Jianfeng Zhu 001; Shouyi Yin; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2020)

Jintide: Utilizing Low-Cost Reconfigurable External Monitors to Substantially Enhance Hardware Security of Large-Scale CPU Clusters. - Jianfeng Zhu 001; Ao Luo; Guanhua Li; Bowei Zhang 002; Yong Wang; Gang Shan; Yi Li; Jianfeng Pan; Chenchen Deng; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE J. Solid State Circuits, 2021)

An Elastic Task Scheduling Scheme on Coarse-Grained Reconfigurable Architectures. - Longlong Chen; Jianfeng Zhu 001; Yangdong Deng; Zhaoshi Li; Jian Chen; Xiaowei Jiang; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Parallel Distributed Syst., 2021)

Software Defined Chips - Volume I, 2 - Shaojun Wei; Leibo Liu; Jianfeng Zhu 001; Chenchen Deng (Springer, 2022)

Upward Packet Popup for Deadlock Freedom in Modular Chiplet-Based Systems. - Yibo Wu; Liang Wang 020; Xiaohang Wang 001; Jie Han 001; Jianfeng Zhu 001; Honglan Jiang; Shouyi Yin; Shaojun Wei; Leibo Liu (HPCA, 2022)

CaSMap: agile mapper for reconfigurable spatial architectures by automatically clustering intermediate representations and scattering mapping process. - Xingchen Man; Jianfeng Zhu 001; Guihuan Song; Shouyi Yin; Shaojun Wei; Leibo Liu (ISCA, 2022)

An energy-efficient dynamically reconfigurable cryptographic engine with improved power/EM-side-channel-attack resistance. - Chenchen Deng; Min Zhu 001; Jinjiang Yang; Youyu Wu; Jiaji He; Bohan Yang 001; Jianfeng Zhu 001; Shouyi Yin; Shaojun Wei; Leibo Liu (Sci. China Inf. Sci., 2022)

Dynamic-II Pipeline: Compiling Loops With Irregular Branches on Static-Scheduling CGRA. - Baofen Yuan; Jianfeng Zhu 001; Xingchen Man; Zijiao Ma; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Orinoco: Ordered Issue and Unordered Commit with Non-Collapsible Queues. - Dibei Chen; Tairan Zhang; Yi Huang; Jianfeng Zhu 001; Yang Liu 326; Pengfei Gou; Chunyang Feng; Binghua Li; Shaojun Wei; Leibo Liu (ISCA, 2023)

MapZero: Mapping for Coarse-grained Reconfigurable Architectures with Reinforcement Learning and Monte-Carlo Tree Search. - Xiangyu Kong; Yi Huang; Jianfeng Zhu 001; Xingchen Man; Yang Liu 326; Chunyang Feng; Pengfei Gou; Minggui Tang; Shaojun Wei; Leibo Liu (ISCA, 2023)

Shogun: A Task Scheduling Framework for Graph Mining Accelerators. - Yibo Wu; Jianfeng Zhu 001; Wenrui Wei; Longlong Chen; Liang Wang 020; Shaojun Wei; Leibo Liu (ISCA, 2023)

CASA: An Energy-Efficient and High-Speed CAM-based SMEM Seeding Accelerator for Genome Alignment. - Yi Huang; Lingkun Kong; Dibei Chen; Zhiyu Chen 003; Xiangyu Kong; Jianfeng Zhu 001; Konstantinos Mamouras; Shaojun Wei; Kaiyuan Yang 001; Leibo Liu (MICRO, 2023)

M2STaR: A Multimode Spatio-Temporal Redundancy Design for Fault-Tolerant Coarse-Grained Reconfigurable Architectures. - Xiangyu Kong; Jianfeng Zhu 001; Xingchen Man; Guihuan Song; Yi Huang; Chenchen Deng; Pengfei Gou; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

QuickFPS: Architecture and Algorithm Co-Design for Farthest Point Sampling in Large-Scale Point Clouds. - Meng Han; Liang Wang 020; Limin Xiao; Hao Zhang; Chenhao Zhang; Xiangrong Xu; Jianfeng Zhu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

GEM: Ultra-Efficient Near-Memory Reconfigurable Acceleration for Read Mapping by Dividing and Predictive Scattering. - Longlong Chen; Jianfeng Zhu 001; Guiqiang Peng; Mingxu Liu; Shaojun Wei; Leibo Liu (IEEE Trans. Parallel Distributed Syst., 2023)

Harp: Leveraging Quasi-Sequential Characteristics to Accelerate Sequence-to-Graph Mapping of Long Reads. - Yichi Zhang; Dibei Chen; Gang Zeng; Jianfeng Zhu 001; Zhaoshi Li; Longlong Chen; Shaojun Wei; Leibo Liu (ASPLOS (3), 2024)

CATCAM: a 28 nm constant-time alteration TCAM enabling less than 50 ns update latency. - Chenchen Deng; Tianzhu Xiong; Zhaoshi Li; Zhiwei Liu; Yao Wang; Jianfeng Zhu 001; Jun Yang 006; Shaojun Wei; Leibo Liu (Sci. China Inf. Sci., 2024)

UpWB: An Uncoupled Architecture Design for White-box Cryptography Using Vectorized Montgomery Multiplication. - Xiangren Chen; Bohan Yang 001; Jianfeng Zhu 001; Jun Liu; Shuying Yin; Guang Yang; Min Zhu 001; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024)

A High-Performance Genomic Accelerator for Accurate Sequence-to-Graph Alignment Using Dynamic Programming Algorithm. - Gang Zeng; Jianfeng Zhu 001; Yichi Zhang; Ganhui Chen; Zhenhai Yuan; Shaojun Wei; Leibo Liu (IEEE Trans. Parallel Distributed Syst., 2024)

EFFACT: A Highly Efficient Full-Stack FHE Acceleration Platform. - Yi Huang; Xinsheng Gong; Xiangyu Kong; Dibei Chen; Jianfeng Zhu 001; Wenping Zhu; Liangwei Li; Mingyu Gao 001; Shaojun Wei; Aoyang Zhang; Leibo Liu (HPCA, 2025)

Lincoln: Real-Time 50 100B LLM Inference on Consumer Devices with LPDDR-Interfaced, Compute-Enabled Flash Memory. - Weiyi Sun; Mingyu Gao 001; Zhaoshi Li; Aoyang Zhang; Iris Ying Chou; Jianfeng Zhu 001; Shaojun Wei; Leibo Liu (HPCA, 2025)

Software-defined process-near-memory architecture using 3D hybrid bonding integration. - Anlin Xu; Chenchen Deng; Jianfeng Zhu 001; Yao Wang; Shaojun Wei; Leibo Liu (Sci. China Inf. Sci., 2025)

Raccoon: Lightweight Support for Comprehensive Control Flows in Reconfigurable Spatial Architectures. - Xiangyu Kong; Yi Huang; Longlong Chen; Jianfeng Zhu 001; Liangwei Li; Xingchen Man; Mingyu Gao 001; Shaojun Wei; Leibo Liu (IEEE Trans. Parallel Distributed Syst., 2025)

A 28-nm Software-Defined Accelerator Chip With Circuit-Pipeline Scaling and Intrinsic Physical Unclonable Function Enabling Secure Configuration. - Jianfeng Zhu 001; Bohan Yang 001; Longlong Chen; Jinyi Chen; Yong Zhang; Liangwei Li; Liwei Zhang; Hanning Wang; Shaojun Wei; Leibo Liu (IEEE J. Solid State Circuits, 2025)

SSS-DIMM: Removing Redundant Data Movement in Trusted DIMM-Based Near-Memory-Processing Kernel Offloading via Secure Space Sharing. - Weiyi Sun; Jianfeng Zhu 001; Mingyu Gao 001; Zhaoshi Li; Shaojun Wei; Leibo Liu (IEEE Trans. Parallel Distributed Syst., 2025)