Collective Test Generation and Test Set Compaction. - Jiang Chau Wang; Edward P. Stabler (ISCAS, 1995)

A Methodology for Minimum Area Cellular Automata Generation. - Paulo Sérgio Cardoso; Marius Strum; José Roberto de A. Amazonas; Jiang Chau Wang (Asian Test Symposium, 1998)

Exploring Concurrency in Data Path Functional Units BIST Plan Optimization: A Study-Case. - José Roberto de A. Amazonas; Marius Strum; Wang Jiang Chau (SBCCI, 1998)

Architectural Transformations for Hierarchical Algorithmic Descriptions. - Marcio Yukio Teruya; Marius Strum; Jiang Chau Wang (VLSI, 1999)

Self Test Built-in Plan for Data-Path Functional Units. - Jose Artur Quilici González; José Roberto de A. Amazonas; Marius Strum; Wang Jiang Chau (LATW, 2000)

Synthesis of High Performance Extended Burst Mode Asynchronous State Machines. - Duarte Lopes de Oliveira; Marius Strum; Wang Jiang Chau; Wagner Chiepa Cunha (SBCCI, 2000)

Synthesis of Multi-Burst Controllers as Modified Huffman Machines. - Duarte Lopes de Oliveira; Wagner Chiepa Cunha; Marius Strum; Wang Jiang Chau (SBCCI, 2001)

A Comparison Between Test Pattern Generation Strategies for Functional Units in BIST Applications. - Wang Jiang Chau; Paulo Sérgio Cardoso; Marius Strum; Ricardo Pires (LATW, 2002)

BIST Plan Optimization and Independent Input Test Register Insertion for Datapath Functional Units. - Wang Jiang Chau; Jose Artur Quilici González; Marius Strum; Ricardo Pires (LATW, 2002)

Miriã: a CAD tool to synthesize multi-burst controllers for heterogeneous systems. - Duarte Lopes de Oliveira; Marius Strum; Jiang Chau Wang; Wagner Chiepa Cunha (Microelectron. Reliab., 2003)

Datapath BIST Insertion Using Pre-Characterized Area and Testability Data. - Jiang Chau Wang; Paulo Sérgio Cardoso; Jose Artur Quilici González; Marius Strum; Ricardo Pires (J. Electron. Test., 2004)

Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor. - Edgar Leonardo Romero; Marius Strum; Jiang Chau Wang (CODES+ISSS, 2005)

A Dynamically Reconfigurable Bluetooth Base Band Unit. - John Esquiagola; Guilherme Ozari; Marcio Yukio Teruya; Marius Strum; Jiang Chau Wang (FPL, 2005)

Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. - Duarte Lopes de Oliveira; Marius Strum; Jiang Chau Wang (SBCCI, 2005)

A System-level Performance Evaluation Methodology for Network Processors Based on Network Calculus Analytical Modeling. - Frederico De Faria; Marius Strum; Jiang Chau Wang (ISVLSI, 2007)

The Multiple Pairs SMO: A modified SMO algorithm for the acceleration of the SVM training. - Raul Acosta Hernandez; Marius Strum; Jiang Chau Wang; Jose Artur Quilici González (IJCNN, 2009)

A PD-based methodology to enhance efficiency in testbenches with random stimulation. - Carlos Ivan Castro Marquez; Marius Strum; Jiang Chau Wang (SBCCI, 2009)

Automatic generation of a parameter-domain-based functional input coverage model. - Carlos Ivan Castro Marquez; Marius Strum; Wang Jiang Chau (LATW, 2010)

The LRD traffic impact on the NoC-based SoCs. - Johanna Sepúlveda; Marius Strum; Jiang Chau Wang; Ricardo Pires (SBCCI, 2010)

Implementation of QoSS (Quality-of-Security Service) for NoC-Based SoC Protection. - Johanna Sepúlveda; Ricardo Pires; Marius Strum; Jiang Chau Wang (Trans. Comput. Sci., 2010)

Formally verifying an RTOS scheduling monitor IP core in embedded systems. - Carlos Ivan Castro Marquez; Marius Strum; Wang Jiang Chau; Fabian Vargas 001 (LATW, 2011)

Dynamic NoC-based architecture for MPSoC security implementation. - Johanna Sepúlveda; Guy Gogniat; Ricardo Pires; Jiang Chau Wang; Marius Strum (SBCCI, 2011)

A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling. - Carlos Ivan Castro Marquez; Edgar Leonardo Romero Tobar; Marius Strum; Jiang Chau Wang (J. Electron. Test., 2011)

Multi-objective artificial immune algorithm for security-constrained multi-application NoC mapping. - Martha Johanna Sepúlveda; Jiang Chau Wang; Marius Strum; César Pedraza; Guy Gogniat; Ricardo Pires (GECCO (Companion), 2012)

Hybrid-on-chip communication architecture for dynamic MP-SoC protection. - Johanna Sepúlveda; Guy Gogniat; Ricardo Pires; Jiang Chau Wang; Marius Strum (SBCCI, 2012)

Workload and task characterization based on operation modes timing analysis. - Gustavo A. Patiño-Álvarez; Jorge González; Jiang Chau Wang; Marius Strum (SoCC, 2012)

QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection. - Johanna Sepúlveda; Ricardo Pires; Guy Gogniat; Jiang Chau Wang; Marius Strum (Int. J. Reconfigurable Comput., 2012)

3DMIA: a multi-objective artificial immune algorithm for 3D-MPSoC multi-application 3D-NoC mapping. - Martha Johanna Sepúlveda; Guy Gogniat; Daniel Mauricio Sepúlveda; Ricardo Pires; Jiang Chau Wang; Marius Strum (GECCO (Companion), 2013)

Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions. - Carlos Ivan Castro Marquez; Marius Strum; Jiang Chau Wang (IDT, 2013)

A strategy for mapping reconfigurable cores in NoCs. - Jonas Gomes Filho; Marius Strum; Wang Jiang Chau (LASCAS, 2013)

Long range dependence in intrachip transaction level traffic. - Jorge González; Gustavo A. Patiño-Álvarez; Marius Strum; Wang Jiang Chau (LASCAS, 2013)

QoS 3D-HoC hybrid-on-chip communication structure for dynamic 3D-MPSoCs. - Johanna Sepúlveda; Guy Gogniat; Ricardo Pires; César Pedraza; Wang Jiang Chau; Marius Strum (LASCAS, 2013)

Formal equivalence checking between high-level and RTL hardware designs. - Carlos Ivan Castro Marquez; Marius Strum; Jiang Chau Wang (LATW, 2013)

PrOCov: Probabilistic output coverage model. - Joel Ivan Munoz Quispe; Marius Strum; Jiang Chau Wang (LATW, 2013)

Exploring the problems of placement and mapping in NoC-based reconfizurable systems. - Jonas Gomes Filho; Jiang Chau Wang (ReConFig, 2013)

Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protection. - Johanna Sepúlveda; Guy Gogniat; Ricardo Pires; Jiang Chau Wang; Marius Strum (SBCCI, 2013)

An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs. - Johanna Sepúlveda; Guy Gogniat; Ricardo Pires; Jiang Chau Wang; Marius Strum (SBCCI, 2013)

Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification. - Edgar Leonardo Romero; Marius Strum; Jiang Chau Wang (J. Electron. Test., 2013)

A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designs. - Carlos Ivan Castro Marquez; Marius Strum; Jiang Chau Wang (LATW, 2014)

DyAFNoC: Characterization and analysis of a dynamically reconfigurable NoC using a DOR-based deadlock-free routing algorithm. - Ernesto Villegas Castillo; Gabriele Miorandi; Jiang Chau Wang (NOCS, 2014)

DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost. - Ernesto Villegas Castillo; Gabriele Miorandi; Davide Bertozzi; Jiang Chau Wang (ARC, 2015)

Dynamically Reconfigurable NoC using a deadlock-free flexible routing algorithm with a low hardware implementation cost. - Ernesto Villegas Castillo; Jiang Chau Wang; Gabriele Miorandi; Davide Bertozzi (LASCAS, 2015)

Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLS. - Raul Acosta Hernandez; Marius Strum; Jiang Chau Wang (LATS, 2015)

A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification Models. - Carlos Ivan Castro Marquez; Marius Strum; Jiang Chau Wang (J. Electron. Test., 2015)

Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems. - Jonas Gomes Filho; Marius Strum; Jiang Chau Wang (Int. J. Reconfigurable Comput., 2015)

Scenario-Aware Workload Characterization Based on a Max-Plus Linear Representation. - Gustavo A. Patiño-Álvarez; Jiang Chau Wang (FORMATS, 2016)

Intra-chip traffic generation under autoregressive models based on time series obtained by TLM simulation. - Jose Eduardo Chiarelli Bueno Filho; Jorge Luis Gonzalez Reano; Jiang Chau Wang (SoCC, 2016)

Mixed signal verification to avoid integration mismatch in complex SoCs. - Vinicius Martins; Jiang Chau Wang; Jerson Paulo Guex (LATS, 2017)

Multifractal on-chip traffic generation under TLM. - Jose Eduardo Chiarelli Bueno Filho; Jiang Chau Wang (SoCC, 2017)

On TLM traffic accuracy: A multifractal perspective. - Jose Eduardo Chiarelli Bueno Filho; Wang Jiang Chau (LASCAS, 2018)

The functional verification of a satellite transponder. - Vinicius Martins; Jerson Paulo Guex; Luciana Shiroma Montali; Jiang Chau Wang (LASCAS, 2018)

Mapping and Placement in NoC-based Reconfigurable Systems Using an Adaptive Tabu Search Algorithm. - Guilherme Apolinario Silva Novaes; Luiz Carlos Moreira; Wang Jiang Chau (LASCAS, 2019)

Exploring Tabu search based algorithms for mapping and placement in NoC-based reconfigurable systems. - Guilherme Apolinario Silva Novaes; Luiz Carlos Moreira; Wang Jiang Chau (SBCCI, 2019)

Accelerating the base-level alignment step of DNA assembling in Minimap2 Algorithm using FPGA. - Carolina Teng; Renan W. Achjian; Caio C. Braga; Marcelo Knörich Zuffo; Wang Jiang Chau (LASCAS, 2021)