Wave pipelining for application-specific networks-on-chips. - Jiang Xu 001; Wayne H. Wolf (CASES, 2002)

A wave-pipelined on-chip interconnect structure for networks-on-chips. - Jiang Xu 001; Wayne H. Wolf (Hot Interconnects, 2003)

Augmenting Platform-Based Design with Synthesis Tools. - Yuan Xie 001; Jiang Xu 001; Wayne H. Wolf (J. Circuits Syst. Comput., 2003)

A Case Study in Networks-on-Chip Design for Embedded Video. - Jiang Xu 001; Wayne H. Wolf; Jörg Henkel; Srimat T. Chakradhar; Tiehan Lv (DATE, 2004)

H.264 HDTV Decoder Using Application-Specific Networks-On-Chip. - Jiang Xu 001; Wayne H. Wolf; Jörg Henkel; Srimat T. Chakradhar (ICME, 2005)

A methodology for design, modeling, and analysis of networks-on-chip. - Jiang Xu 001; Wayne H. Wolf; Jörg Henkel; Srimat T. Chakradhar (ISCAS (2), 2005)

A Methodology for Architectural Design of Multimedia Multiprocessor SoCs. - Tiehan Lv; Jiang Xu 001; Wayne H. Wolf; I. Burak Özer; Jörg Henkel; Srimat T. Chakradhar (IEEE Des. Test Comput., 2005)

A design methodology for application-specific networks-on-chip. - Jiang Xu 001; Wayne H. Wolf; Jörg Henkel; Srimat T. Chakradhar (ACM Trans. Embed. Comput. Syst., 2006)

A novel optical mesh network-on-chip for gigascale systems-on-chip. - Huaxi Gu; Jiang Xu 001; Zheng Wang (APCCAS, 2008)

ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip. - Huaxi Gu; Jiang Xu 001; Zheng Wang (CODES+ISSS, 2008)

3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC). - Yaoyao Ye; Lian Duan; Jiang Xu 001; Jin Ouyang; Mo Kwai Hung; Yuan Xie 001 (3DIC, 2009)

A case study of on-chip sensor network in multiprocessor system-on-chip. - Yu Wang 002; Jiang Xu 001; Shengxi Huang; Weichen Liu; Huazhong Yang (CASES, 2009)

An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking. - Weichen Liu; Zonghua Gu 001; Jiang Xu 001; Yu Wang 002; Mingxuan Yuan (CODES+ISSS, 2009)

A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip. - Huaxi Gu; Jiang Xu 001; Wei Zhang 012 (DATE, 2009)

A Novel Multiple Description Video Coding based on H.264/AVC Video Coding Standard. - Xing Wen; Oscar C. Au; Jiang Xu 001; Zhiqin Liang; Yi Yang 041; Weiran Tang (ISCAS, 2009)

A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip. - Huaxi Gu; Mo Kwai Hung Morton; Jiang Xu 001; Wei Zhang 012 (ISVLSI, 2009)

On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise. - Yan Xu; Weichen Liu; Yu Wang 002; Jiang Xu 001; Xiaoming Chen 003; Huazhong Yang (ISVLSI, 2009)

Efficient Software Synthesis for Dynamic Single Appearance Scheduling of Synchronous Dataflow. - Weichen Liu; Zonghua Gu 001; Jiang Xu 001 (IEEE Embed. Syst. Lett., 2009)

Efficient algorithms for 2D area management and online task placement on runtime reconfigurable FPGAs. - Zonghua Gu 001; Weichen Liu; Jiang Xu 001; Jin Cui; Xiuqiang He 001; Qingxu Deng (Microprocess. Microsystems, 2009)

Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs. - Jiang Xu 001; Wayne H. Wolf; Wei Zhang 012 (IEEE Micro, 2009)

Crosstalk noise and bit error rate analysis for optical network-on-chip. - Yiyuan Xie; Mahdi Nikdast; Jiang Xu 001; Wei Zhang 012; Qi Li 013; Xiaowen Wu; Yaoyao Ye; Xuan Wang 001; Weichen Liu (DAC, 2010)

A highly data reusable and standard-compliant motion estimation hardware architecture. - Xing Wen; Oscar C. Au; Jiang Xu 001; Lu Fang 001; Run Cha; Jiali Li (ICME, 2010)

A Hierarchical Hybrid Optical-Electronic Network-on-Chip. - Mo Kwai Hung; Yaoyao Ye; Xiaowen Wu; Wei Zhang 012; Weichen Liu; Jiang Xu 001 (ISVLSI, 2010)

UNION: A unified inter/intra-chip optical network for chip multiprocessors. - Xiaowen Wu; Yaoyao Ye; Wei Zhang 012; Weichen Liu; Mahdi Nikdast; Xuan Wang 001; Jiang Xu 001 (NANOARCH, 2010)

A new distributed congestion control mechanism for networks on chip. - Huaxi Gu; Jiang Xu 001; Kun Wang 001; Mo Kwai Hung Morton (Telecommun. Syst., 2010)

Sub-pixel downsampling of video with matching highly data re-use hardware architecture. - Xing Wen; Oscar C. Au; Jiang Xu 001; Lu Fang 001; Run Cha (ISCAS, 2011)

A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC. - Weichen Liu; Jiang Xu 001; Xuan Wang 001; Yu Wang 002; Wei Zhang 012; Yaoyao Ye; Xiaowen Wu; Mahdi Nikdast; Zhehui Wang (ISVLSI, 2011)

A NoC Traffic Suite Based on Real Applications. - Weichen Liu; Jiang Xu 001; Xiaowen Wu; Yaoyao Ye; Xuan Wang 001; Wei Zhang 012; Mahdi Nikdast; Zhehui Wang (ISVLSI, 2011)

Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip. - Yaoyao Ye; Jiang Xu 001; Xiaowen Wu; Wei Zhang 012; Xuan Wang 001; Mahdi Nikdast; Zhehui Wang; Weichen Liu (ISVLSI, 2011)

Coroutine-Based Synthesis of Efficient Embedded Software From SystemC Models. - Weichen Liu; Jiang Xu 001; Jogesh K. Muppala; Wei Zhang 012; Xiaowen Wu; Yaoyao Ye (IEEE Embed. Syst. Lett., 2011)

Novel RD-Optimized VBSME With Matching Highly Data Re-Usable Hardware Architecture. - Xing Wen; Oscar C. Au; Jiang Xu 001; Lu Fang 001; Run Cha; Jiali Li (IEEE Trans. Circuits Syst. Video Technol., 2011)

Satisfiability Modulo Graph Theory for Task Mapping and Scheduling on Multiprocessor Systems. - Weichen Liu; Zonghua Gu 001; Jiang Xu 001; Xiaowen Wu; Yaoyao Ye (IEEE Trans. Parallel Distributed Syst., 2011)

Power Gating Aware Task Scheduling in MPSoC. - Yu Wang 002; Jiang Xu 001; Yan Xu; Weichen Liu; Huazhong Yang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip. - Yaoyao Ye; Jiang Xu 001; Xiaowen Wu; Wei Zhang 012; Weichen Liu; Mahdi Nikdast (ACM J. Emerg. Technol. Comput. Syst., 2012)

Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories. - Xuan Wang 001; Jiang Xu 001; Wei Zhang 012; Xiaowen Wu; Yaoyao Ye; Zhehui Wang; Mahdi Nikdast; Zhe Wang 003 (DATE, 2013)

System-level analysis of mesh-based hybrid optical-electronic network-on-chip. - Yaoyao Ye; Xiaowen Wu; Jiang Xu 001; Mahdi Nikdast; Zhehui Wang; Xuan Wang 001; Zhe Wang 003 (ISCAS, 2013)

A formal study on topology and floorplan characteristics of mesh and torus-based optical networks-on-chip. - Kai Feng; Yaoyao Ye; Jiang Xu 001 (Microprocess. Microsystems, 2013)

Many-cores and On-chip Interconnects (NII Shonan Meeting 2013-8). - Tomohiro Yoneda; José Flich Cardo; Jiang Xu 001; Michihiro Koibuchi (NII Shonan Meet. Rep., 2013)

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip. - Yaoyao Ye; Jiang Xu 001; Baihan Huang; Xiaowen Wu; Wei Zhang 012; Xuan Wang 001; Mahdi Nikdast; Zhehui Wang; Weichen Liu; Zhe Wang 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip. - Weichen Liu; Yu Wang 002; Xuan Wang 001; Jiang Xu 001; Huazhong Yang (IEEE Trans. Parallel Distributed Syst., 2013)

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip. - Yiyuan Xie; Mahdi Nikdast; Jiang Xu 001; Xiaowen Wu; Wei Zhang 012; Yaoyao Ye; Xuan Wang 001; Zhehui Wang; Weichen Liu (IEEE Trans. Very Large Scale Integr. Syst., 2013)

System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip. - Yaoyao Ye; Jiang Xu 001; Xiaowen Wu; Wei Zhang 012; Xuan Wang 001; Mahdi Nikdast; Zhehui Wang; Weichen Liu (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A systematic network-on-chip traffic modeling and generation methodology. - Zhe Wang 003; Weichen Liu; Jiang Xu 001; Xiaowen Wu; Zhehui Wang; Bin Li 018; Ravi R. Iyer 001; Ramesh Illikkal (APCCAS, 2014)

Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors. - Xuan Wang 001; Jiang Xu 001; Zhe Wang 003; Kevin J. Chen; Xiaowen Wu; Zhehui Wang (DATE, 2014)

A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs. - Zhe Wang 003; Weichen Liu; Jiang Xu 001; Bin Li 018; Ravi R. Iyer 001; Ramesh Illikkal; Xiaowen Wu; Wai Ho Mow; Wenjing Ye (ISVLSI, 2014)

CLAP: a crosstalk and loss analysis platform for optical interconnects. - Mahdi Nikdast; Luan H. K. Duong; Jiang Xu 001; Sébastien Le Beux; Xiaowen Wu; Zhehui Wang; Peng Yang 003; Yaoyao Ye (NOCS, 2014)

Introduction to the special session on "Silicon photonic interconnects: an illusion or a realistic solution?". - Jiang Xu 001; Sébastien Le Beux; Yvain Thonnart (NOCS, 2014)

A Case Study of Signal-to-Noise Ratio in Ring-Based Optical Networks-on-Chip. - Luan H. K. Duong; Mahdi Nikdast; Sébastien Le Beux; Jiang Xu 001; Xiaowen Wu; Zhehui Wang; Peng Yang 003 (IEEE Des. Test, 2014)

On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip. - Weichen Liu; Xuan Wang 001; Jiang Xu 001; Wei Zhang 012; Yaoyao Ye; Xiaowen Wu; Mahdi Nikdast; Zhehui Wang (ACM J. Emerg. Technol. Comput. Syst., 2014)

SUOR: Sectioned Undirectional Optical Ring for Chip Multiprocessor. - Xiaowen Wu; Jiang Xu 001; Yaoyao Ye; Zhehui Wang; Mahdi Nikdast; Xuan Wang 001 (ACM J. Emerg. Technol. Comput. Syst., 2014)

Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors. - Zhehui Wang; Jiang Xu 001; Xiaowen Wu; Yaoyao Ye; Wei Zhang 012; Mahdi Nikdast; Xuan Wang 001; Zhe Wang 003 (IEEE Trans. Computers, 2014)

Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip. - Mahdi Nikdast; Jiang Xu 001; Xiaowen Wu; Wei Zhang 012; Yaoyao Ye; Xuan Wang 001; Zhehui Wang; Zhe Wang 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip. - Yaoyao Ye; Zhehui Wang; Peng Yang 003; Jiang Xu 001; Xiaowen Wu; Xuan Wang 001; Mahdi Nikdast; Zhe Wang 003; Luan H. K. Duong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors. - Xiaowen Wu; Yaoyao Ye; Jiang Xu 001; Wei Zhang 012; Weichen Liu; Mahdi Nikdast; Xuan Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Alleviate chip I/O pin constraints for multicore processors through optical interconnects. - Zhehui Wang; Jiang Xu 001; Peng Yang 003; Xuan Wang 001; Zhe Wang 003; Luan H. K. Duong; Zhifei Wang; Haoran Li 002; Rafael Kioji Vivas Maeda; Xiaowen Wu; Yaoyao Ye; Qinfen Hao (ASP-DAC, 2015)

Coherent crosstalk noise analyses in ring-based optical interconnects. - Luan H. K. Duong; Mahdi Nikdast; Jiang Xu 001; Zhehui Wang; Yvain Thonnart; Sébastien Le Beux; Peng Yang 003; Xiaowen Wu; Zhifei Wang (DATE, 2015)

Adaptively tolerate power-gating-induced power/ground noise under process variations. - Zhe Wang 003; Xuan Wang 001; Jiang Xu 001; Xiaowen Wu; Zhehui Wang; Peng Yang 003; Luan H. K. Duong; Haoran Li 002; Rafael Kioji Vivas Maeda; Zhifei Wang (DATE, 2015)

Memory Access Analysis of Many-core System with Abundant Bandwidth. - Chuan Tang; Dan Liu; Zuocheng Xing; Peng Yang 003; Zhe Wang 003; Jiang Xu 001 (MCSoC, 2015)

An Improved Content-Based Music Recommending Method with Weighted Tags. - Lu Ding; Ning Zheng 001; Jiang Xu 001; Ming Xu 001 (MMM (1), 2015)

An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators. - Xuan Wang 001; Jiang Xu 001; Zhe Wang 003; Kevin J. Chen; Xiaowen Wu; Zhehui Wang; Peng Yang 003; Luan H. K. Duong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint. - Mahdi Nikdast; Jiang Xu 001; Luan H. K. Duong; Xiaowen Wu; Zhehui Wang; Xuan Wang 001; Zhe Wang 003 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison. - Mahdi Nikdast; Jiang Xu 001; Luan Huu Kinh Duong; Xiaowen Wu; Xuan Wang 001; Zhehui Wang; Zhe Wang 003; Peng Yang 003; Yaoyao Ye; Qinfen Hao (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC. - Xuan Wang 001; Jiang Xu 001; Wei Zhang 012; Xiaowen Wu; Yaoyao Ye; Zhehui Wang; Mahdi Nikdast; Zhe Wang 003 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

An Inter/Intra-Chip Optical Network for Manycore Processors. - Xiaowen Wu; Jiang Xu 001; Yaoyao Ye; Xuan Wang 001; Mahdi Nikdast; Zhehui Wang; Zhe Wang 003 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models. - Rafael K. V. Maeda; Peng Yang 003; Xiaowen Wu; Zhe Wang 003; Jiang Xu 001; Zhehui Wang; Haoran Li 002; Luan H. K. Duong; Zhifei Wang (AISTECS@HiPEAC, 2016)

Inter/intra-chip optical interconnection network: opportunities, challenges, and implementations. - Peng Yang 003; Shigeru Nakamura; Kenichiro Yashiki; Zhehui Wang; Luan H. K. Duong; Zhifei Wang; Xuanqi Chen; Yuichi Nakamura 002; Jiang Xu 001 (NOCS, 2016)

Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign. - Xuan Wang 001; Jiang Xu 001; Zhe Wang 003; Haoran Li 002; Peng Yang 003; Luan H. K. Duong; Rafael K. V. Maeda; Zhifei Wang (ACM J. Emerg. Technol. Comput. Syst., 2016)

Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks. - Luan H. K. Duong; Zhehui Wang; Mahdi Nikdast; Jiang Xu 001; Peng Yang 003; Zhifei Wang; Zhe Wang 003; Rafael K. V. Maeda; Haoran Li 002; Xuan Wang 001; Sébastien Le Beux; Yvain Thonnart (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip. - Weichen Liu; Wei Zhang 012; Xuan Wang 001; Jiang Xu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC. - Zhe Wang 003; Xuan Wang 001; Jiang Xu 001; Haoran Li 002; Rafael K. V. Maeda; Zhehui Wang; Peng Yang 003; Luan H. K. Duong; Zhifei Wang (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects. - Zhehui Wang; Jiang Xu 001; Peng Yang 003; Luan Huu Kinh Duong; Zhifei Wang; Xuan Wang 001; Zhe Wang 003; Haoran Li 002; Rafael Kioji Vivas Maeda (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Improve Chip Pin Performance Using Optical Interconnects. - Zhehui Wang; Jiang Xu 001; Peng Yang 003; Xuan Wang 001; Zhe Wang 003; Luan Huu Kinh Duong; Zhifei Wang; Rafael Kioji Vivas Maeda; Haoran Li 002 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Modular reinforcement learning for self-adaptive energy efficiency optimization in multicore system. - Zhe Wang 003; Zhongyuan Tian; Jiang Xu 001; Rafael K. V. Maeda; Haoran Li 002; Peng Yang 003; Zhehui Wang; Luan H. K. Duong; Zhifei Wang; Xuanqi Chen (ASP-DAC, 2017)

MOCA: an Inter/Intra-Chip Optical Network for Memory. - Zhehui Wang; Zhengbin Pang; Peng Yang 003; Jiang Xu 001; Xuanqi Chen; Rafael K. V. Maeda; Zhifei Wang; Luan H. K. Duong; Haoran Li 002; Zhe Wang 003 (DAC, 2017)

Adaptive power delivery system management for many-core processors with on/off-chip voltage regulators. - Haoran Li 002; Jiang Xu 001; Zhe Wang 003; Peng Yang 003; Rafael K. V. Maeda; Zhongyuan Tian (DATE, 2017)

Fast and Accurate Exploration of Multi-level Caches Using Hierarchical Reuse Distance. - Rafael K. V. Maeda; Qiong Cai; Jiang Xu 001; Zhe Wang 003; Zhongyuan Tian (HPCA, 2017)

Thermal-sensitive design and power optimization for a 3D torus-based optical NoC. - Kang Yao; Yaoyao Ye; Sudeep Pasricha; Jiang Xu 001 (ICCAD, 2017)

Energy-Efficient Power Delivery System Paradigms for Many-Core Processors. - Haoran Li 002; Xuan Wang 001; Jiang Xu 001; Zhe Wang 003; Rafael K. V. Maeda; Zhehui Wang; Peng Yang 003; Luan H. K. Duong; Zhifei Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Editorial. - Krishnendu Chakrabarty; Massimo Alioto; Bevan M. Baas; Chirn Chye Boon; Meng-Fan Chang; Naehyuck Chang; Yao-Wen Chang; Chip-Hong Chang; Shih-Chieh Chang; Poki Chen; Masud H. Chowdhury; Pasquale Corsonello; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Multi-device collaborative management through knowledge sharing. - Zhongyuan Tian; Zhe Wang 003; Haoran Li 002; Peng Yang 003; Rafael Kioji Vivas Maeda; Jiang Xu 001 (ASP-DAC, 2018)

RSON: An inter/intra-chip silicon photonic network for rack-scale computing systems. - Peng Yang 003; Zhengbin Pang; Zhifei Wang; Zhehui Wang; Min Xie; Xuanqi Chen; Luan H. K. Duong; Jiang Xu 001 (DATE, 2018)

Co-manage power delivery and consumption for manycore systems using reinforcement learning. - Haoran Li 002; Zhongyuan Tian; Rafael K. V. Maeda; Xuanqi Chen; Jun Feng 008; Jiang Xu 001 (ICCAD, 2018)

Decentralized Collaborative Power Management through Multi-Device Knowledge Sharing. - Zhongyuan Tian; Haoran Li 002; Rafael Kioji Vivas Maeda; Jun Feng 008; Jiang Xu 001 (ICCD, 2018)

A Comprehensive Electro-Optical Model for Silicon Photonic Switches. - Xuanqi Chen; Zhifei Wang; Yi-Shing Chang; Jiang Xu 001; Peng Yang 003; Zhehui Wang; Luan H. K. Duong (ISVLSI, 2018)

Silicon Photonics for Computing Systems. - Jiang Xu 001; Yuichi Nakamura 002; Andrew B. Kahng (ACM J. Emerg. Technol. Comput. Syst., 2018)

Workload-Aware Adaptive Power Delivery System Management for Many-Core Processors. - Haoran Li 002; Jiang Xu 001; Zhe Wang 003; Rafael K. V. Maeda; Peng Yang 003; Zhongyuan Tian (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Systematic and Realistic Network-on-Chip Traffic Modeling and Generation Technique for Emerging Many-Core Systems. - Weichen Liu; Zhe Wang 003; Peng Yang 003; Jiang Xu 001; Bin Li 018; Ravi R. Iyer 001; Ramesh Illikkal (IEEE Trans. Multi Scale Comput. Syst., 2018)

Systematic Exploration of High-Radix Integrated Silicon Photonic Switches for Datacenters. - Zhifei Wang; Jun Feng 008; Xuanqi Chen; Zhehui Wang; Jiaxu Zhang; Shixi Chen; Jiang Xu 001 (ICCAD, 2019)

Scalable Low-Power High-Performance Rack-Scale Optical Network. - Jun Feng 008; Zhehui Wang; Zhifei Wang; Xuanqi Chen; Shixi Chen; Jiaxu Zhang; Jiang Xu 001 (PHOTONICS@SC, 2019)

Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks. - Luan H. K. Duong; Peng Yang 003; Zhifei Wang; Yi-Shing Chang; Jiang Xu 001; Zhehui Wang; Xuanqi Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Collaborative Power Management Through Knowledge Sharing Among Multiple Devices. - Zhongyuan Tian; Zhe Wang 003; Jiang Xu 001; Haoran Li 002; Peng Yang 003; Rafael Kioji Vivas Maeda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. - Massimo Alioto; Magdy S. Abadir; Tughrul Arslan; Chirn Chye Boon; Andreas Burg 001; Chip-Hong Chang; Meng-Fan Chang; Yao-Wen Chang; Poki Chen; Pasquale Corsonello; Paolo Crovetti; Shiro Dosho; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Efficient Optical Power Delivery System for Hybrid Electronic-Photonic Manycore Processors. - Shixi Chen; Jiang Xu 001; Xuanqi Chen; Zhifei Wang; Jun Feng 008; Jiaxu Zhang; Zhongyuan Tian; Xiao Li (DATE, 2020)

Modeling and Analysis of Optical Modulators Based on Free-Carrier Plasma Dispersion Effect. - Xuanqi Chen; Zhifei Wang; Yi-Shing Chang; Jiang Xu 001; Jun Feng 008; Peng Yang 003; Zhehui Wang; Luan H. K. Duong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

CAMON: Low-Cost Silicon Photonic Chiplet for Manycore Processors. - Zhehui Wang; Zhifei Wang; Jiang Xu 001; Yi-Shing Chang; Jun Feng 008; Xuanqi Chen; Shixi Chen; Jiaxu Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A Cross-Layer Optimization Framework for Integrated Optical Switches in Data Centers. - Zhifei Wang; Peng Yang 003; Yi-Shing Chang; Jiang Xu 001; Xuanqi Chen; Zhehui Wang; Jun Feng 008 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Multidomain Inter/Intrachip Silicon Photonic Networks for Energy-Efficient Rack-Scale Computing Systems. - Peng Yang 003; Zhehui Wang; Zhifei Wang; Jiang Xu 001; Yi-Shing Chang; Xuanqi Chen; Rafael K. V. Maeda; Jun Feng 008 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Chip-Specific Power Delivery and Consumption Co-Management for Process-Variation-Aware Manycore Systems Using Reinforcement Learning. - Haoran Li 002; Zhongyuan Tian; Jiang Xu 001; Rafael K. V. Maeda; Zhehui Wang; Zhifei Wang (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Multidevice Collaborative Power Management Through Decentralized Knowledge Sharing. - Zhongyuan Tian; Jiang Xu 001; Haoran Li 002; Rafael Kioji Vivas Maeda (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Rejuvenate Post-Moore's Law Computing with Photonics-Electronics Hybrid Systems. - Jun Feng 008; Shixi Chen; Jiaxu Zhang; Jiang Xu 001 (ICICDT, 2021)

Multi-Core Power Management through Deep Reinforcement Learning. - Zhongyuan Tian; Lin Chen 029; Xiao Li; Jun Feng 008; Jiang Xu 001 (ISCAS, 2021)

Simultaneously Tolerate Thermal and Process Variations Through Indirect Feedback Tuning for Silicon Photonic Networks. - Xuanqi Chen; Jun Feng 008; Jiang Xu 001; Jiaxu Zhang; Shixi Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Reduce Loss and Crosstalk in Integrated Silicon-Photonic Multistage Switching Fabrics Through Multichip Partition. - Zhehui Wang; Zhifei Wang; Jiang Xu 001; Jun Feng 008; Shixi Chen; Xuanqi Chen; Jiaxu Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

PHANES: ReRAM-based photonic accelerator for deep neural networks. - Yinyi Liu; Jiaqi Liu; Yuxiang Fu; Shixi Chen; Jiaxu Zhang; Jiang Xu 001 (DAC, 2022)

Improve the Stability and Robustness of Power Management through Model-free Deep Reinforcement Learning. - Lin Chen 029; Xiao Li; Jiang Xu 001 (DATE, 2022)

A Reliability Concern on Photonic Neural Networks. - Yinyi Liu; Jiaxu Zhang; Jun Feng 008; Shixi Chen; Jiang Xu 001 (DATE, 2022)

Accelerating Cache Coherence in Manycore Processor through Silicon Photonic Chiplet. - Chengeng Li; Fan Jiang; Shixi Chen; Jiaxu Zhang; Yinyi Liu; Yuxiang Fu; Jiang Xu 001 (ICCAD, 2022)

Energy-Efficient High-Performance Photonic Backplane Network for Rack-Scale Computing Systems. - Jun Feng 008; Shixi Chen; Jiaxu Zhang; Yuxiang Fu; Jiang Xu 001 (ISVLSI, 2022)

Power Management for Chiplet-Based Multicore Systems Using Deep Reinforcement Learning. - Xiao Li; Lin Chen 029; Shixi Chen; Fan Jiang; Chengeng Li; Jiang Xu 001 (ISVLSI, 2022)

Reduce Footprints of Multiport Interferometers by Cosine-Sine-Decomposition Unfolding. - Yinyi Liu; Jiaxu Zhang; Jun Feng 008; Shixi Chen; Jiang Xu 001 (OFC, 2022)

Improving the thermal reliability of photonic chiplets on multicore processors. - Xuanqi Chen; Yuxiang Fu; Jun Feng 008; Jiaxu Zhang; Shixi Chen; Jiang Xu 001 (Integr., 2022)

HERO: Pbit High-Radix Optical Switch Based on Integrated Silicon Photonics for Data Center. - Zhifei Wang; Jun Feng 008; Jiang Xu 001; Xuanqi Chen; Jiaxu Zhang; Shixi Chen; Yinyi Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Fast and Accurate Statistical Simulation of Shared-Memory Applications on Multicore Systems. - Fan Jiang; Rafael K. V. Maeda; Jun Feng 008; Shixi Chen; Lin Chen 029; Xiao Li; Jiang Xu 001 (IEEE Trans. Parallel Distributed Syst., 2022)

Smart Knowledge Transfer-based Runtime Power Management. - Lin Chen 029; Xiao Li; Fan Jiang; Chengeng Li; Jiang Xu 001 (DATE, 2023)

RONet: Scaling GPU System with Silicon Photonic Chiplet. - Chengeng Li; Fan Jiang; Shixi Chen; Xianbin Li; Yinyi Liu; Lin Chen 029; Xiao Li; Jiang Xu 001 (ICCAD, 2023)

FIONA: Photonic-Electronic CoSimulation Framework and Transferable Prototyping for Photonic Accelerator. - Yinyi Liu; Bohan Hu; Zhenguo Liu; Peiyu Chen; Linfeng Du; Jiaqi Liu; Xianbin Li; Wei Zhang 012; Jiang Xu 001 (ICCAD, 2023)

Memory Workload Synthesis Using Generative AI. - Chengao Shi; Fan Jiang; Zhenguo Liu; Chen Ding 001; Jiang Xu 001 (MEMSYS, 2023)

PhotonNTT: Energy-Efficient Parallel Photonic Number Theoretic Transform Accelerator. - Xianbin Li; Jiaqi Liu; Yuying Zhang; Yinyi Liu; Jiaxu Zhang; Chengeng Li; Shixi Chen; Yuxiang Fu; Fengshi Tian; Wei Zhang 012; Jiang Xu 001 (DATE, 2024)

NEOCNN: NTT-Enabled Optical Convolution Neural Network Accelerator. - Xianbin Li; Yinyi Liu; Fan Jiang; Chengeng Li; Yuxiang Fu; Wei Zhang 012; Jiang Xu 001 (ICS, 2024)

Towards Thermally Reliable Photonic Links for Multicore Processors. - Yuxiang Fu; Xuanqi Chen; Jiaxu Zhang; Shixi Chen; Jiang Xu 001 (ISVLSI, 2024)

PC-oriented Prediction-based Runtime Power Management for GPGPU using Knowledge Transfer. - Lin Chen 029; Xiao Li; Shixi Chen; Fan Jiang; Chengeng Li; Wei Zhang 012; Jiang Xu 001 (SPAA, 2024)

Deep Reinforcement Learning-Based Power Management for Chiplet-Based Multicore Systems. - Xiao Li; Lin Chen 029; Shixi Chen; Fan Jiang; Chengeng Li; Wei Zhang 012; Jiang Xu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

PCBAgent: An Agent-based Framework for High-Density Printed Circuit Board Placement. - Lin Chen 029; Ran Chen 001; Shoubo Hu; Xufeng Yao; Zhentao Tang; Shixiong Kai; Siyuan Xu; Mingxuan Yuan; Jianye Hao; Bei Yu 001; Jiang Xu 001 (ASP-DAC, 2025)

Invited paper: SPICE-Compatible Modeling and Design for Electronic-Photonic Integrated Circuits. - Yuxiang Fu; Yinyi Liu; Ngai Wong 001; Jiang Xu 001 (ASP-DAC, 2025)

SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge Devices. - Yipu Zhang; Jiawei Liang; Jian Peng; Jiang Xu 001; Wei Zhang 012 (DATE, 2025)