A 1.83 μW, 0.78 μVrms input referred noise neural recording front end. - Jiangchao Wu; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (ISCAS, 2013)

A 2-µW 45-nV/√Hz Readout Front End With Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop. - Jiangchao Wu; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Fully Integrated High Voltage Pulse Driver Using Switched-Capacitor Voltage Multiplier and Synchronous Charge Compensation in 65-nm CMOS. - Jiangchao Wu; Ka-Chon Lei; Hou-Man Leong; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Low Complexity Illumination-Invariant Motion Vector Detection Based on Logarithmic Edge Detection and Edge Difference. - Chuanqi Wei; Jiangchao Wu; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (ISCAS, 2020)

A Fully Integrated 10-V Pulse Driver Using Multiband Pulse-Frequency Modulation in 65-nm CMOS. - Jiangchao Wu; Hou-Man Leong; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2021)

High Linearity BJT-Based Time-Domain CMOS Temperature Sensor. - Yu Lei; Qishen Fang; Jiangchao Wu; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (APCCAS, 2022)

Fully Integrated Reconfigurable Solar Energy Harvester for $100 mu mathrm{A}$ Burst Output Current Delivery with 78.6% Peak Energy Extraction Efficiency and Minimum Startup Incident Light Power of 0.27mW/cm2. - Jiangchao Wu; Guangshu Zhao; Litao Zhang; Yu Jia; Yang Jiang 002; Pui-In Mak; Rui Paulo Martins; Man Kay Law (A-SSCC, 2023)

A 0.9V CMOS Voltage Reference with 0.41% Untrimmed Accuracy and 44.7 ppm/°C TC from -35°C to 130°C. - Xuanlin Chen; Jiangchao Wu; Bo Wang 012; Man Kay Law (A-SSCC, 2024)

A 33.6nW Capacitively Coupled Chopper Amplifier with Stacked Input-Boosted Gate-and-Bulk-Driven Inverter Achieving 0.59 NEF and 0.42 PEF in 180nm CMOS. - Ke Hu; Jiangchao Wu; Bo Wang 012; Man Kay Law (A-SSCC, 2024)

A 0.25pJ/Comparison, 27.3μV Input Noise Dynamic Comparator Exploiting Stacked Floating Preamplifier with Cross-Coupled Feedback Inverters in 180nm CMOS. - Jiangchao Wu; Ke Hu; Xuanlin Chen; Pui-In Mak; Rui Paulo Martins; Man Kay Law (CICC, 2024)

A 93.4% Peak Efficiency CLOAD-Free Multi-Phase Switched-Capacitor DC-DC Converter Achieving a Fast DVS up to 222.5 mV/ns. - Feiyu Li; Qishen Fang; Jiangchao Wu; Yang Jiang 002; Pui-In Mak; Rui Paulo Martins; Man-Kay Law (IEEE J. Solid State Circuits, 2024)

A 0.013 mm² 3.2-ns Input Range 10-Bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65-nm CMOS. - Xin Lu; Jiangchao Wu; Zhao Wang; Yifei Xiang; Liyuan Liu; Pui-In Mak; Rui Paulo Martins; Man-Kay Law (IEEE Trans. Circuits Syst. II Express Briefs, 2024)