YHFT-QDSP: High-Performance Heterogeneous Multi-Core DSP. - Shuming Chen; Jianghua Wan; Jianzhuang Lu; Zhong Liu; Hai-Yan Sun; Yong-Jie Sun; Hengzhu Liu; Xiang-Yuan Liu; Zhentao Li; Yi Xu; Xiaowen Chen (J. Comput. Sci. Technol., 2010)

Design and chip implementation of a heterogeneous multi-core DSP. - Shuming Chen; Xiaowen Chen; Yi Xu; Jianghua Wan; Jianzhuang Lu; Xiangyuan Liu; Shenggang Chen (ASP-DAC, 2011)

AIFSP: An Adaptive Instruction Flow Stream Processor. - Yaohua Wang; Shuming Chen; Jianghua Wan; Kai Zhang 023; Shenggang Chen (ISVLSI, 2011)

Matrix Odd-Even Partition: A High Power-Efficient Solution to the Small Grain Data Shuffle. - Sheng Liu 001; Shuming Chen; Jianghua Wan; Haiyan Chen; Yaohua Wang (NAS, 2011)

LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs. - Sheng Liu 001; Shuming Chen; Xi Ning; Jianghua Wan; Hu Chen; Kai Zhang 023; Yaohua Wang (IEICE Electron. Express, 2011)

Architectural Implications for SIMD Processors in the Wireless Communication Domain. - Yaohua Wang; Kai Zhang 023; Jianghua Wan; Sheng Liu 001; Xi Ning; Shuming Chen (HPCC-ICESS, 2012)

Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures. - Yaohua Wang; Shuming Chen; Kai Zhang 023; Jianghua Wan; Xiaowen Chen; Hu Chen; Haibo Wang 004 (IEEE Comput. Archit. Lett., 2012)

A cost conscious performance model for media processors. - Yaohua Wang; Shuming Chen; Kai Zhang 023; Jianghua Wan; Hu Chen; Sheng Liu 001; Xi Ning (IEICE Electron. Express, 2012)

A multiple SIMD, multiple data (MSMD) architecture: Parallel execution of dynamic and static SIMD fragments. - Yaohua Wang; Shuming Chen; Jianghua Wan; Jiayuan Meng; Kai Zhang 023; Wei Liu 013; Xi Ning (HPCA, 2013)

Redefining the relationship between scalar and parallel units in SIMD architectures. - Yaohua Wang; Shuming Chen; Jianghua Wan; Kai Zhang 023 (ISCAS, 2013)

Real-Time Implementation of 4x4 MIMO-OFDM System for 3GPP-LTE Based on a Programmable Processor. - Ting Chen; Hengzhu Liu; Jianghua Wan (NCCET, 2013)

Decoupled iteration mapping: improving dependency-loop performance on SIMD processors. - Hui Yang; Shuming Chen; Jianghua Wan; Huanyao Dai (IEICE Electron. Express, 2013)

Breaking the performance bottleneck of sparse matrix-vector multiplication on SIMD processors. - Kai Zhang 023; Shuming Chen; Yaohua Wang; Jianghua Wan (IEICE Electron. Express, 2013)

Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures. - Yaohua Wang; Shuming Chen; Hu Chen; Jianghua Wan; Kai Zhang 023; Sheng Liu 001 (IEICE Trans. Inf. Syst., 2013)

FT-Matrix: A Coordination-Aware Architecture for Signal Processing. - Shuming Chen; Yaohua Wang; Sheng Liu 001; Jianghua Wan; Haiyan Chen; Hengzhu Liu; Kai Zhang 023; Xiangyuan Liu; Xi Ning (IEEE Micro, 2014)

Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs. - Xiaowen Chen; Zhonghai Lu; Yang Li; Axel Jantsch; Xueqian Zhao; Shuming Chen; Yang Guo 003; Zonglin Liu; Jianzhuang Lu; Jianghua Wan; Shuwei Sun; Shenggang Chen; et al. (ISVLSI, 2015)

Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs. - Sheng Liu 001; Haiyan Chen; Jianghua Wan; Yaohua Wang (ISVLSI, 2016)