New Linearization Implementations Improving IIP3 of Wideband LNTA by More than 14dB. - Cong Tao; Liangbo Lei; Jiangli Huang; Zhipeng Chen; Yumei Huang; Zhiliang Hong (ASICON, 2021)

A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization. - Jiangli Huang; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (ASP-DAC, 2021)

Bayesian Optimization Approach for Analog Circuit Design Using Multi-Task Gaussian Process. - Jiangli Huang; Shuhan Zhang; Cong Tao; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (ISCAS, 2021)

An Analog Circuit Building Block Generator via Nested Multi-Fidelity Modeling. - Jiangli Huang; Chuyu Wang; Yuyang Yan; Cong Tao; Fan Yang 001; Changhao Yan; Wenchuang Walter Hu; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Automatic Op-Amp Generation From Specification to Layout. - Jialin Lu; Liangbo Lei; Jiangli Huang; Fan Yang 001; Li Shang; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Artisan: Automated Operational Amplifier Design via Domain-specific Large Language Model. - Zihao Chen; Jiangli Huang; Yiting Liu; Fan Yang 001; Li Shang; Dian Zhou; Xuan Zeng 001 (DAC, 2024)

A Compact 0.1-1.95 GHz, 1.5 dB NF LNTA Based on Cascode Inverters. - Cong Tao; Jiangli Huang; Liangbo Lei; Yumei Huang; Zhiliang Hong; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2024)