DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization. - Vivek Govindaraj; Jianglin Du; Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (APCCAS, 2019)

A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS. - Jianglin Du; Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (CICC, 2019)

17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM. - Yizhe Hu; Xi Chen 070; Teerachot Siriburanon; Jianglin Du; Zhong Gao; Vivek Govindaraj; Anding Zhu; Robert Bogdan Staszewski (ISSCC, 2020)

A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter-N of -269.3 dB. - Jianglin Du; Teerachot Siriburanon; Xi Chen 070; Yizhe Hu; Vivek Govindaraj; Anding Zhu; Robert Bogdan Staszewski (VLSI Circuits, 2021)

A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL. - Jianglin Du; Teerachot Siriburanon; Yizhe Hu; Vivek Govindaraj; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2021)

A Type-II Phase-Tracking Receiver. - Suoping Hu; Jianglin Du; Peng Chen 022; Hieu Minh Nguyen; Philip Quinlan; Teerachot Siriburanon; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2021)

Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS. - Ali Esmailiyan; Jianglin Du; Teerachot Siriburanon; Filippo Schembari; Robert Bogdan Staszewski (IEEE Open J. Circuits Syst., 2021)

A Compact 0.2-0.3-V Inverse-Class-F23 Oscillator for Low 1/f3 Noise Over Wide Tuning Range. - Jianglin Du; Yizhe Hu; Teerachot Siriburanon; Enis Kobal; Philip Quinlan; Anding Zhu; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2022)

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking. - Yizhe Hu; Xi Chen 070; Teerachot Siriburanon; Jianglin Du; Vivek Govindaraj; Anding Zhu; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2022)

Flicker Phase-Noise Reduction Using Gate-Drain Phase Shift in Transformer-Based Oscillators. - Xi Chen 070; Yizhe Hu; Teerachot Siriburanon; Jianglin Du; Robert Bogdan Staszewski; Anding Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness. - Xi Chen 070; Yizhe Hu; Teerachot Siriburanon; Jianglin Du; Robert Bogdan Staszewski; Anding Zhu (IEEE J. Solid State Circuits, 2023)

A Low-Noise Digital-to-Time Converter Exploiting Waveform of Integrated Crystal Oscillator. - Teerachot Siriburanon; Xi Chen 070; Chunxiao Liu; Jianglin Du; Anding Zhu; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2025)