Optimization of QDR SRAM Controller in Network Processor. - Kang Li; Hongye Jia; Honghu Gong; Jiangyi Shi; Peijun Ma (ISCID (1), 2011)

SRNoC: A novel high performance Shared-Resource routing scheme for Network-on-Chip. - Hao Shu; Peijun Ma; Jiangyi Shi; Zhao Xu; Lin-An Yang (Microelectron. J., 2014)

A High-Throughput VLSI Architecture Design of Arithmetic Encoder in JPEG2000. - Zhixiong Di; Yue Hao 001; Jiangyi Shi; Peijun Ma (J. Signal Process. Syst., 2015)

A monopulse scheme in Radar angle-measurement based on Beam-Comparison. - Jiangyi Shi; Hongwei Liu 001; Peijun Ma (CISP-BMEI, 2016)

Dual priority congestion aware shared-resource Network-on-Chip architecture. - Hao Shu; Jiangyi Shi; Peijun Ma; Huaxi Gu; Weitao Pan; Lin-An Yang (IEICE Electron. Express, 2016)

High Parallel VLSI Architecture Design of BPC in JPEG2000. - Lintao Li; Jiangyi Shi; Zhixiong Di (ASICON, 2019)

A self-clocked binary-seaching digital low-dropout regulator with fast transient response. - Jiangyi Shi; Bo Zhao; Zhengguang Tang; Peijun Ma; Zhixiong Di (IEICE Electron. Express, 2020)

A local congestion elimination technique driven by overflow. - Wei Wu; Zhixiong Di; Jiangyi Shi; Quanyuan Feng; Zhengguang Tang (IEICE Electron. Express, 2020)

Recent progress of integrated circuits and optoelectronic chips. - Yue Hao 001; Shuiying Xiang; Genquan Han; Jincheng Zhang; Xiaohua Ma 001; Zhangming Zhu; Xingxing Guo; Yahui Zhang; Yanan Han; Ziwei Song; Yan Liu; Ling Yang 003; et al. (Sci. China Inf. Sci., 2021)

Hardware Trojan Designs Based on High-Low Probability and Partitioned Combinational Logic With a Malicious Reset Signal. - Jiangyi Shi; Xinyuan Zhang; Peijun Ma; Weitao Pan; Pengfei Li; Zhengguang Tang (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Learned Compression Framework With Pyramidal Features and Quality Enhancement for SAR Images. - Zhixiong Di; Xuan Chen; Qiang Wu; Jiangyi Shi; Quanyuan Feng; Yibo Fan (IEEE Geosci. Remote. Sens. Lett., 2022)

Synthetic Aperture Radar Image Compression Based on a Variational Autoencoder. - Qihan Xu; Yunfan Xiang; Zhixiong Di; Yibo Fan; Quanyuan Feng; Qiang Wu; Jiangyi Shi (IEEE Geosci. Remote. Sens. Lett., 2022)

NBLG: A Robust Legalizer for Mixed-Cell-Height Modern Design. - Jinwei Chen; Zhixiong Di; Jiangyi Shi; Quanyuan Feng; Qiang Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Detailed Routing Short Violation Prediction Using Graph-Based Deep Learning Model. - Xuan Chen; Zhixiong Di; Wei Wu; Qiang Wu; Jiangyi Shi; Quanyuan Feng (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Broadband Amplifier With Flat Bandwidth for Modulator and Measurement Driver Circuits. - Yuchen Wang; Xiaohua Ma 001; Yang Lu; Bochao Zhao; Ziyue Zhao; Chupeng Yi; Ling Yang 003; Jiangyi Shi; Yue Hao 001 (IEEE Trans. Instrum. Meas., 2022)

A VLSI Architecture for MQ Arithmetic Encoder Supporting Three-Context Parallel Processing. - Peijun Ma; Cong Yao; Jiangyi Shi; Gongzhi Zhao (ICVISP, 2024)

GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features. - Peijun Ma; Ge Shang; Hongjin Liu; Jiangyi Shi; Weitao Pan; Yan Zhang; Yue Hao 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Corrections to "GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features". - Peijun Ma; Ge Shang; Hongjin Liu; Jiangyi Shi; Weitao Pan; Yan Zhang; Yue Hao 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Hardware Trojan Detection Methods for Gate-Level Netlists Based on Graph Neural Networks. - Peijun Ma; Jie Li; Hongjin Liu; Jiangyi Shi; Shaolin Zhang; Weitao Pan; Yue Hao 001 (IEEE Trans. Computers, 2025)

Design of a Timer Queue Supporting Dynamic Update Operations. - Zekun Wang; Binghao Yue; Weitao Pan; Jiangyi Shi; Yue Hao (CoRR, 2025)