Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual- Vdd CGRAs. - Shouyi Yin; Jiangyuan Gu; Dajiang Liu; Leibo Liu; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Energy-aware loops mapping on multi-vdd CGRAs without performance degradation. - Jiangyuan Gu; Shouyi Yin; Leibo Liu; Shaojun Wei (ASP-DAC, 2017)

Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect. - Jiangyuan Gu; Shouyi Yin; Shaojun Wei (DAC, 2017)

Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory. - Shouyi Yin; Xianqing Yao; Tianyi Lu; Dajiang Liu; Jiangyuan Gu; Leibo Liu; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2017)

A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications. - Shouyi Yin; Peng Ouyang; Shibin Tang; Fengbin Tu; Xiudong Li; Shixuan Zheng; Tianyi Lu; Jiangyuan Gu; Leibo Liu; Shaojun Wei (IEEE J. Solid State Circuits, 2018)

Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration. - Jiangyuan Gu; Shouyi Yin; Leibo Liu; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2018)

TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. - Mingyang Kou; Jiangyuan Gu; Shaojun Wei; Hailong Yao; Shouyi Yin (DAC, 2020)

Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs. - Cheng Li; Jiangyuan Gu; Shouyi Yin; Leibo Liu; Shaojun Wei (ASP-DAC, 2021)

A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating. - Song Zhang; Jiangyuan Gu; Shouyi Yin; Leibo Liu; Shaojun Wei (ASP-DAC, 2021)

Mixed-granularity parallel coarse-grained reconfigurable architecture. - Jinyi Deng; Linyun Zhang; Lei Wang; Jiawei Liu; Kexiang Deng; Shibin Tang; Jiangyuan Gu; Boxiao Han; Fei Xu; Leibo Liu; Shaojun Wei; Shouyi Yin (DAC, 2022)

GEML: GNN-based efficient mapping method for large loop applications on CGRA. - Mingyang Kou; Jun Zeng; Boxiao Han; Fei Xu; Jiangyuan Gu; Hailong Yao (DAC, 2022)

RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA. - Qidie Wu; Jiangyuan Gu; Youxu Lin; Boxiao Han; Hongjun He; Yang Hu 001; Leibo Liu; Shaojun Wei; Shouyi Yin (DAC, 2023)

WindMill: A Parameterized and Pluggable CGRA Implemented by DIAG Design Flow. - Haojia Hui; Jiangyuan Gu; Xunbo Hu; Yang Hu 001; Leibo Liu; Shaojun Wei; Shouyi Yin (CoRR, 2023)

TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. - Mingyang Kou; Jiangyuan Gu; Hailong Yao; Shaojun Wei; Shouyi Yin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

DIAG: A Refined Four-layer Agile Hardware Developing Flow for Generating Flexible Reconfigurable Architectures. - Haojia Hui; Jiangyuan Gu; Xunbo Hu; Shaojun Wei; Shouyi Yin (ASP-DAC, 2025)

Computing Efficiency Improvement for Multi-PEA CGRA with Built-in Control Design. - Jiangyuan Gu; Xunbo Hu; Zidi Qin; Shaojun Wei; Shouyi Yin (CF, 2025)