LADPM: Latency-Aware Dual-Partition Multicast Routing for Mesh-Based Network-on-Chips. - Jianhua Li 003; Chun Jason Xue; Yinlong Xu (ICPADS, 2010)

ExLRU: a unified write buffer cache management for flash memory. - Liang Shi 001; Jianhua Li 003; Chun Jason Xue; Chengmo Yang; Xuehai Zhou (EMSOFT, 2011)

Exploiting set-level write non-uniformity for energy-efficient NVM-based hybrid cache. - Jianhua Li 003; Liang Shi 001; Chun Jason Xue; Chengmo Yang; Yinlong Xu (ESTIMedia, 2011)

Optimal task allocation on non-volatile memory based hybrid main memory. - Wanyong Tian; Jianhua Li 003; Yingchao Zhao 001; Chun Jason Xue; Minming Li; Enhong Chen (RACS, 2011)

STT-RAM based energy-efficiency hybrid cache for CMPs. - Jianhua Li 003; Chun Jason Xue; Yinlong Xu (VLSI-SoC, 2011)

TEACA: Thread ProgrEss Aware Coherence Adaption for hybrid coherence protocols. - Jianhua Li 003; Liang Shi 001; Qing'an Li; Chun Jason Xue; Yinlong Xu (ESTIMedia, 2012)

MAC: migration-aware compilation for STT-RAM based hybrid cache in embedded systems. - Qing'an Li; Jianhua Li 003; Liang Shi 001; Chun Jason Xue; Yanxiang He (ISLPED, 2012)

Code Motion for Migration Minimization in STT-RAM Based Hybrid Cache. - Qing'an Li; Liang Shi 001; Jianhua Li 003; Chun Jason Xue; Yanxiang He (ISVLSI, 2012)

Hybrid nonvolatile disk cache for energy-efficient and high-performance systems. - Liang Shi 001; Jianhua Li 003; Chun Jason Xue; Xuehai Zhou (ACM Trans. Design Autom. Electr. Syst., 2012)

Cache coherence enabled adaptive refresh for volatile STT-RAM. - Jianhua Li 003; Liang Shi 001; Qing'an Li; Chun Jason Xue; Yiran Chen 001; Yinlong Xu (DATE, 2013)

Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh. - Jianhua Li 003; Liang Shi 001; Qing'an Li; Chun Jason Xue; Yiran Chen 001; Yinlong Xu; Wei Wang 237 (ACM Trans. Design Autom. Electr. Syst., 2013)

Cooperating Virtual Memory and Write Buffer Management for Flash-Based Storage Systems. - Liang Shi 001; Jianhua Li 003; Chun Jason Xue; Xuehai Zhou (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Task Allocation on Nonvolatile-Memory-Based Hybrid Main Memory. - Wanyong Tian; Yingchao Zhao 001; Liang Shi 001; Qing'an Li; Jianhua Li 003; Chun Jason Xue; Minming Li; Enhong Chen (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Dual partitioning multicasting for high-performance on-chip networks. - Jianhua Li 003; Liang Shi 001; Chun Jason Xue; Yinlong Xu (J. Parallel Distributed Comput., 2014)

Thread Progress Aware Coherence Adaption for Hybrid Cache Coherence Protocols. - Jianhua Li 003; Liang Shi 001; Qing'an Li; Chun Jason Xue; Yinlong Xu (IEEE Trans. Parallel Distributed Syst., 2014)

WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture. - Yazhi Huang; Liang Shi 001; Jianhua Li 003; Qing'an Li; Chun Jason Xue (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Compiler-Assisted STT-RAM-Based Hybrid Cache for Energy Efficient Embedded Systems. - Qing'an Li; Jianhua Li 003; Liang Shi 001; Mengying Zhao; Chun Jason Xue; Yanxiang He (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A Unified Write Buffer Cache Management Scheme for Flash Memory. - Liang Shi 001; Jianhua Li 003; Qing'an Li; Chun Jason Xue; Chengmo Yang; Xuehai Zhou (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache. - Qing'an Li; Yanxiang He; Jianhua Li 003; Liang Shi 001; Yiran Chen 001; Chun Jason Xue (IEEE Trans. Computers, 2015)

Thread Criticality Assisted Replication and Migration for Chip Multiprocessor Caches. - Jianhua Li 003; Minming Li; Chun Jason Xue; Yiming Ouyang; Fanfan Shen (IEEE Trans. Computers, 2017)

NVLH: Crash-Consistent Linear Hashing for Non-Volatile Memory. - Hu Wan 001; Fuyang Li; Zimeng Zhou; Kaisheng Zeng; Jianhua Li 003; Chun Jason Xue (NVMSA, 2018)

Design of Low-Power WiNoC with Congestion-Aware Wireless Node. - Yiming Ouyang; Zhe Li; Kun Xing; Zhengfeng Huang; Huaguo Liang; Jianhua Li 003 (J. Circuits Syst. Comput., 2018)

Reuse locality aware cache partitioning for last-level cache. - Fanfan Shen; Yanxiang He; Jun Zhang 058; Qingan Li; Jianhua Li 003; Chao Xu (Comput. Electr. Eng., 2019)

CPCA: An efficient wireless routing algorithm in WiNoC for cross path congestion awareness. - Yiming Ouyang; Zhe Li; Jianhua Li 003; Chenglong Sun; Huaguo Liang; Gaoming Du (Integr., 2019)

Design of Wireless Network on Chip with Priority-Based MAC. - Yiming Ouyang; Yang Zhao; Kun Xing; Zhengfeng Huang; Huaguo Liang; Jianhua Li 003 (J. Circuits Syst. Comput., 2019)

A Novel Low-Latency Regional Fault-Aware Fault-Tolerant Routing Algorithm for Wireless NoC. - Yiming Ouyang; Qi Wang 027; Mengxuan Ru; Huaguo Liang; Jianhua Li 003 (IEEE Access, 2020)

WiGRUNT: WiFi-Enabled Gesture Recognition Using Dual-Attention Network. - Yu Gu 003; Xiang Zhang 011; Yantong Wang; Meng Wang 001; Huan Yan; Yusheng Ji; Zhi Liu 002; Jianhua Li 003; Mianxiong Dong (IEEE Trans. Hum. Mach. Syst., 2022)

A transparent virtual channel power gating method for on-chip network routers. - Wu Zhou; Yiming Ouyang; Jianhua Li 003; Dongyu Xu (Integr., 2023)

Transit ring: bubble flow control for eliminating inter-ring communication congestion. - Yiming Ouyang; Chenglong Sun; Ruifeng Li; Qi Wang 027; Jianhua Li 003 (J. Supercomput., 2023)

A tree-recursive partitioned multicast mechanism for NoC-based deep neural network accelerator. - Yiming Ouyang; Yihe Zhang; Huaguo Liang; Jianhua Li 003 (Microelectron. J., 2024)

Fault-tolerant routing for reliable packet transmission in on-chip networks. - Yiming Ouyang; Tianbao Zhang; Jianhua Li 003; Huaguo Liang (Microelectron. J., 2024)

Thermal Safe Power Constrained Dynamic Mapping for Heterogeneous Multicore System. - Ling Wang; Huayong Wei; Yun Qi; Jianhua Li 003 (J. Circuits Syst. Comput., 2024)

F-Bypass: A Low-Power Network-on-Chip Design Utilizing Bypass to Improve Network Connectivity. - Yiming Ouyang; Shuaijie Yuan; Jianhua Li 003; Huaguo Liang (ACM J. Emerg. Technol. Comput. Syst., 2024)

PRLM: A parallel loading mechanism for a deep neural network accelerator based on NoC. - Yiming Ouyang; Chengming An; Jianhua Li 003; Huaguo Liang (Microelectron. J., 2025)

Fabdb: a low-latency fault-tolerant architecture based on dynamic bypass for network-on-chip. - Yiming Ouyang; Zhuoxuan Ji; Jianhua Li 003; Huaguo Liang (J. Supercomput., 2025)