Monolithic transformers and their application in a differential CMOS RF low-noise amplifier. - Jianjun Zhou 002; David J. Allstot (IEEE J. Solid State Circuits, 1998)

A 0.25dB gain step high linear programmable gain amplifier. - Xiaobin Shen 003; Taotao Yan; Yuxiao Lu; Jianjun Zhou 002 (ASICON, 2011)

An area-efficient dual-channel RF receiver for GPS-L1/Galileo-E1/Compass-B1. - Hongliang Tian; Dongpo Chen; Tingting Mo; Jianjun Zhou 002 (ASICON, 2011)

Low noise low power two-stage modulator with injection locked LO divider in 65nm CMOS. - Wufeng Wang; Peichen Jiang; Tingting Mo; Jianjun Zhou 002 (ASICON, 2011)

A low-noise WCDMA transmitter with 25%-duty-cycle LO generator in 65nm CMOS. - Haiyi Wang; Peichen Jiang; Tingting Mo; Jianjun Zhou 002 (ASICON, 2011)

A highly linear wideband variable gain CMOS balun-LNA. - Hui Wang 023; Taotao Yan; Dongpo Chen; Jianjun Zhou 002 (ASICON, 2011)

Glitch-Free Multi-Modulus Frequency Divider for Quantization Noise suppression in fractional-N PLLs. - Xiaoming Liu 008; Jing Jin 005; Xi Li; Jianjun Zhou 002 (ISCAS, 2011)

Linear range extensible Phase Frequency Detector and Charge Pump for fast frequency acquisition. - Xiaoming Liu 008; Jing Jin 005; Cui Mao; Jianjun Zhou 002 (ISCAS, 2011)

Adaptive calibration of IIP2 in direct down-conversion mixers with modified LMS algorithm. - Zhijian Lu; Peichen Jiang; Tingting Mo; Jianjun Zhou 002 (ISCAS, 2011)

A Dual-Band GNSS RF Front End With a Pseudo-Differential LNA. - Jun Wu; Peichen Jiang; Dongpo Chen; Jianjun Zhou 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Low-power high-linearity area-efficient multi-mode GNSS RF receiver in 40nm CMOS. - Jinbo Li; Dongpo Chen; Rui Guan; Peng Qin; Zhijian Lu; Jianjun Zhou 002 (ISCAS, 2012)

Anti-interference pseudo-differential wideband LNA for DVB-S.2 RF tuners. - Hui Wang 023; Wufeng Wang; Jing Jin 005; Dongpo Chen; Jianjun Zhou 002 (ISCAS, 2012)

Quantization Noise Suppression in Fractional-N PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider. - Jing Jin 005; Xiaoming Liu 008; Tingting Mo; Jianjun Zhou 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Low jitter clock driver for high-performance pipeline ADC. - Yun Chen; Chaojie Fan; Jianjun Zhou 002 (ASICON, 2013)

Digital calibration techniques for interstage gain nonlinearity in pipelined ADCs. - Chaojie Fan; Wenjie Pan; Ke Wang; Jianjun Zhou 002 (ASICON, 2013)

All-Digital Adaptive Module for Automatic Background IIP2 Calibration in CMOS Downconverters With Fast Convergence. - Peichen Jiang; Zhijian Lu; Rui Guan; Jianjun Zhou 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Injection-Locking Frequency Divider based dual-modulus prescalers with extended locking range. - Jing Jin 005; Bukun Pan; Xiaoming Liu 008; Jianjun Zhou 002 (ISCAS, 2014)

Digital spur calibration of multi-modulus fractional frequency LO divider utilizing most correlated comparison algorithm. - Jing Jin 005; Bukun Pan; Xiaoming Liu 008; Jianjun Zhou 002 (ISCAS, 2014)

A fast low power window-opening logic for high speed SAR ADC. - Yuxiao Lu; Chaojie Fan; Lu Sun; Zhe Li; Jianjun Zhou 002 (IEICE Electron. Express, 2014)

Phase noise suppression techniques for high frequency synthesizers in 65 nm CMOS. - Peng Qin; Hao Yan; Yangyang Zhou; Xiaoyong Li 001; Jianjun Zhou 002 (IEICE Electron. Express, 2014)

A fast and efficient automatic frequency calibration technique for 10 GHz PLLs. - Peng Qin; Yangyang Zhou; Hao Yan; Xiaoyong Li 001; Jianjun Zhou 002 (IEICE Electron. Express, 2014)

A GHz-level ring-counter-based multi-modulus fractional LO divider with on-the-fly tunability. - Bukun Pan; Jing Jin 005; Jianjun Zhou 002 (ASICON, 2015)

A 12-bit 20-MS/s SAR ADC with improved internal clock generator and SAR controller. - Xuan Li; Shuo Huang; Jianjun Zhou 002; Xiaoyong Li 001 (MWSCAS, 2015)

A 14-bit 100 MS/s SHA-less pipelined ADC with 89 dB SFDR and 74.5 dB SNR. - Ke Wang; Chaojie Fan; Wenjie Pan; Jianjun Zhou 002 (IEICE Electron. Express, 2015)

Wideband dual-mode complementary metal-oxide-semiconductor receiver. - Rui Guan; Jing Jin 005; Wenjie Pan; Dongpo Chen; Jianjun Zhou 002 (IET Circuits Devices Syst., 2016)

Analysis of Input LCR Matched N-Path Filter. - Zhijian Lu; Jing Jin 005; Tingting Mo; Jianjun Zhou 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A wideband simplified transformer-based VCO with digital amplitude calibration. - Xinchi Gao; Licheng Xu; Jing Jin 005; Naifeng Jing; Jianjun Zhou 002 (MWSCAS, 2017)

A Reconfigurable 28/56 Gb/s PAM4/NRZ Dual-mode SerDes with Hardware-reuse. - Heng Liu; Li Ding; Jing Jin 005; Jianjun Zhou 002 (ISCAS, 2018)

A 28 Gb/s 2-Tap FFE Source-Series-Terminated Transmitter in 22 nm CMOS FDSOI. - Hanchun Tang; Li Ding; Jing Jin 005; Jianjun Zhou 002 (ISCAS, 2018)

16-bit 1-MS/s SAR ADC with foreground digital-domain calibration. - Rui Guan; Jianfeng Xue; Chao Yang; Jing Jin 005; Jianjun Zhou 002 (IET Circuits Devices Syst., 2018)

A low-cost digital-domain foreground calibration for high resolution SAR ADCs. - Rui Guan; Jing Jin 005; Jianjun Zhou 002 (Microelectron. J., 2018)

Fully Configurable Capacitor-Less Oversampling DC Offset Cancellation for Direct Conversion Receivers. - Jing Jin 005; Xiaoming Liu 008; Taotao Yan; Jianjun Zhou 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 0.25-dB-Step, 68-dB-Dynamic Range Analog Baseband With Digitally Assisted DCOC and AGC for Multi-Standard TV Applications. - Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Low Power Temperature-Compensated Common-Mode Voltage Detector for Dynamic Amplifiers. - Ran Wang; Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Naifeng Jing; Jianjun Zhou 002 (ISCAS, 2020)

An Inverter-Based Continuous Time Sigma Delta ADC With Latency-Free DAC Calibration. - Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou 002 (IEEE Trans. Circuits Syst., 2020)

A Multi-Modulus Fractional Divider With TDC Free Calibration Scheme for Mitigation of TX-VCO Pulling. - Litong Liu; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou 002 (IEEE Trans. Circuits Syst., 2020)

An ISM Band High-Linear Current-Reuse Up-Conversion Mixer With Built-in-Self-Calibration for LOFT and I/Q Imbalance. - Xiaofei Wang; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou 002 (IEEE Trans. Circuits Syst., 2020)

A Phase Domain Excess Loop Delay Compensation Technique with Latency Optimized Phase Selector for VCO-Based Continuous-Time ΔΣ ADC. - Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou 002 (ISCAS, 2021)

A Ka-Band Quadrature-Hybrid LNA-PS with Gm- Boosting Technique in 40-nm CMOS. - Zhengqi Xu; Ke Wu 017; Xiaoming Liu 008; Chengyuan Liu; Jing Jin 005; Jianjun Zhou 002 (ISCAS, 2021)

A Low Power PVT Stabilization Technique for Dynamic Amplifier in Pipelined SAR ADC. - Yuekang Guo; Jing Jin 005; Jianjun Zhou 002 (MWSCAS, 2021)

A Latency-Optimized Lookup Table for Nonlinearity Calibration in VCO-Based Sigma-Delta ADCs. - Yanlin He; Yuekang Guo; Jing Jin 005; Jianjun Zhou 002 (MWSCAS, 2021)

A Linearization Technique for Ring VCO Exploiting Bulk-Modulation. - Qiang Pan; Yuekang Guo; Jing Jin 005; Jianjun Zhou 002 (MWSCAS, 2021)

A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS. - Mengying Hu; Jing Jin 005; Yuekang Guo; Xiaoming Liu 008; Jianjun Zhou 002 (Circuits Syst. Signal Process., 2021)

An 8 GHz real-time temperature-compensated PLL with 20.8 ppm/°C temperature coefficient for SerDes applications. - Li Ding; Ke Wu 017; Jing Jin 005; Jianjun Zhou 002 (Microelectron. J., 2021)

A fully integrated multiphase switched-capacitor DC-DC converter with PFM control and charge sharing loss reduction. - Haopeng Kang; Jing Jin 005; Xiaoming Liu 008; Xiaofei Wang; Pengli Hong; Jianjun Zhou 002 (Microelectron. J., 2021)

A 2.4 GHz receiver with a current-reused inductor-less noise-canceling balun LNA in 40 nm CMOS. - Xiaoming Liu 008; Jing Jin 005; Xiaofei Wang; Jianjun Zhou 002 (Microelectron. J., 2021)

A 38.6-fJ/Conv.-Step Inverter-Based Continuous-Time Bandpass ΔΣ ADC in 28 nm Using Asynchronous SAR Quantizer. - Hanie Ghaedrahmati; Jianjun Zhou 002; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 3bit/cycle 1GS/s 8-bit SAR ADC Employing Asynchronous Ping-Pong Quantization Scheme. - Yuekang Guo; Xiaoming Liu 008; Jing Jin 005; Jianjun Zhou 002 (ISCAS, 2022)

A Power-Efficient CMOS Image Sensor with In-Sensor Processing and In-Pixel Gain Calibration. - Ke Wu 017; Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou 002 (MWSCAS, 2022)

A Harmonic Rejecting N-Path Filter with Harmonic Gain Calibration Technique. - Ran Bu; Jing Jin 005; Zhaolin Yang; Yuekang Guo; Jianjun Zhou 002 (Circuits Syst. Signal Process., 2022)

A 0.023-12 GHz ultra-wideband frequency synthesizer with FOMT of -251.8 dB. - Chao Yang; Xiaoming Liu 008; Jing Jin 005; Jianjun Zhou 002 (Microelectron. J., 2022)

An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC. - Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Fast-Settling Phase-Locked Loop Utilizing Cycle-Slipping-Elimination PFDCP. - Chao Yang; Xiaoming Liu 008; Jing Jin 005; Yuekang Guo; Jianjun Zhou 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver. - Li Ding; Jing Jin 005; Jianjun Zhou 002 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

A High Precision CMOS Temperature Detector with Curvature Calibration Technique. - Weizhen Cai; Jianjun Zhou 002; Xiaobo Chen; Xiaoming Liu 008 (ASICON, 2023)

A 30GHz Bidirectional PA/LNA with Transformer-Based Switchable RC Matching Network. - Hanqi Gao; Jing Jin 005; Zhaolin Yang; Jianjun Zhou 002; Xiaoming Liu 008 (ASICON, 2023)

A Wideband Inductorless LNA Employing Dual-Loop Feedback for Low-Power Applications. - Zhaolin Yang; Jing Jin 005; Yuyang Chen; Jianjun Zhou 002; Xiaoming Liu 008 (ASICON, 2023)

A LUT-based Background Linearization Technique for VCO-based ADC Employing $K_{ text{VCO}}- text{Locked}- text{Loop}$. - Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Zhaolin Yang; Jianjun Zhou 002 (ISCAS, 2023)

A 16/32-Gb/s/pin Dual-Mode Single-Ended Transmitter with Pre-Emphasis FFE and RLM-Enhanced ZQ Calibration for Memory Interfaces. - Xiaofei Wang; Jing Jin 005; Xiaoming Liu 008; Zhaolin Yang; Shan Wang; Jianjun Zhou 002 (ISCAS, 2023)

Predictive LSB-First Successive Approximation for SAR Analog-to-Digital Converters. - Jiayi Chen; Xiaoming Liu 008; Chao Yang; Jing Jin 005; Zhongyuan Chang; Jianjun Zhou 002 (MWSCAS, 2023)

A Non-Linearity Digital Background Calibration Algorithm with Piece-Wise Linear Functions. - Ke Wu 017; Yuekang Guo; Xiaoming Liu 008; Jing Jin 005; Howard C. Yang; Jianjun Zhou 002 (MWSCAS, 2023)

A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction. - Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou 002 (IEEE J. Solid State Circuits, 2023)

A 372 μW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization. - Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou 002 (IEEE J. Solid State Circuits, 2023)

A 4 GHz FLL-less fast-locking sampling PLL with gain-boosted sampling phase-frequency detector in 28 nm CMOS. - Chao Yang; Sheng Wang; Xiaoming Liu 008; Jing Jin 005; Jianjun Zhou 002 (Microelectron. J., 2023)

A 16MHz CMOS RC Frequency Reference with ±125ppm Inaccuracy from -40°C to 85°C Enabled by a Capacitively Modulated RC Time Constant (CMT) Generation and a Die-to-Die Error Removal (DDER) Technique. - Runtao Huo; Dingguo Zhang; Jing Jin 005; Jianjun Zhou 002; Hui Wang 023 (CICC, 2024)

A 470μW 20kHz-BW 107.3dB-SNDR Nested CT DSM Employing Negative-R-Based Cross-RC Filter and Weighted Multi-Threshold MSB-Pass Quantizer. - Jing Jin 005; Yuekang Guo; Meng Xu; Xiaoming Liu 008; Nan Sun 001; Jianjun Zhou 002 (CICC, 2024)

A Self-Calibrated Sampling Noise Cancellation Technique for Noise-Shaping SAR ADC. - Zhengyuan Lou; Meng Xu; Yuekang Guo; Jing Jin 005; Jianjun Zhou 002 (ISCAS, 2024)

A 0.83-pJ/b 20-Gb/s/Pin Single-Ended Transceiver With AC/DC-Coupled Pre-Emphasis FFE and Edge-Dependent Phase-Modulation DFE for Low-Power Memory Controllers. - Xiaofei Wang; Jing Jin 005; Xiaoming Liu 008; Hui Wang 023; Huzhi Tang; Chao Yang; Yuekang Guo; Tingting Mo; Jianjun Zhou 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

An EF-CIFF Noise-Shaping SAR ADC with A Joint Dynamic Amplifier, Comparator and Lossless Passive Summer Structure. - Yuzhi Ai; Yuekang Guo; Zhengyuan Lou; Hui Zhang; Jing Jin 005; Jianjun Zhou 002 (ISCAS, 2025)

A1-GS/s 7-bit 3-then-1 bit/cycle SAR ADC with A Reconfigurable Reference-Embedded Comparator. - Jinwei Wu; Yuekang Guo; Meng Xu; Lingyan Fan; Jing Jin 005; Jianjun Zhou 002 (ISCAS, 2025)

A reconfigurable passive LNA using an N-path switched-capacitor transformer with 2×/3× voltage Gain. - Zhaolin Yang; Xiaoming Liu 008; Jing Jin 005; Jianjun Zhou 002 (Microelectron. J., 2025)

A two-phase oscillation scheme with direct background correction for VCO-based ADC. - Tao Zhong; Yuekang Guo; Jing Jin 005; Jianjun Zhou 002 (Microelectron. J., 2025)

A 0.2-2.6 GHz Reconfigurable Receiver Using RF-Gain-Adapted Impedance Matching and Gm-Separated IQ-Leakage Suppression Structure in 40-nm CMOS. - Zhaolin Yang; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou 002 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Reference Oversampling PLL With a FoMREF of -240.1 dB Enabled By a Capacitive Parasitic-Proof Ring Oscillator and a Time-Multiplexed Gm Stage. - Xueke Cai; Tong Zhang; Yanling Zheng; Li Gao; Jianjun Zhou 002; Howard Yang; Honglan Jiang; Yongfu Li 002; Hui Wang 023 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 470 μW 20 kHz-BW 107.3 dB-SNDR Nested CT DSM Using Negative-R-Based Cross-RC Integrator and Weighted Multi-Threshold MSB-Pass Quantizer. - Jing Jin 005; Meng Xu; Yuekang Guo; Xiaoming Liu 008; Nan Sun 001; Jianjun Zhou 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement. - Ke Wu 017; Yuekang Guo; Xiaoming Liu 008; Zhongyuan Chang; Howard C. Yang; Jing Jin 005; Jianjun Zhou 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 25 MHz-BW 81 dB-DR TDC-Based CTDSM With Background Analog-Integration-Based ISI Error Calibration Achieving >8 dB Even-Order Harmonic Suppression. - Tao Zhong; Yuekang Guo; Jianjun Zhou 002; Hui Zhang; Jing Jin 005 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 5-to-1V DLDO-Hybrid-Sigma Converter Achieving Fast Transient for High-Density Power Delivery. - Zizhe Huang; Yuxiang Li; Yuekang Guo; Jing Jin 005; Jianjun Zhou 002; Junmin Jiang (ASP-DAC, 2026)

A 0.69-pJ/bit 16/24/32-Gb/s/pin NRZ/PAM-3/PAM-4 Multi-Mode Transmitter with Power-Optimal Rx Termination and Clock-Embedded DBI. - Chengrui Gu; Dingguo Zhang; Chao Yang; Jing Jin 005; Howard C. Yang; Jianjun Zhou 002 (ISCAS, 2026)

An energy-efficient 128 Gb/s PAM-4 wireline transmitter with a passive 4:1 MUX in 22 nm CMOS. - Qiang Pan; Yuekang Guo; Chao Yang; Jing Jin 005; Jianjun Zhou 002 (Microelectron. J., 2026)

A 14-bit 1.4 GS/s current-steering DAC with square-dithered frequency-modulated DEM achieving >60-dBc SFDR in 180 nm CMOS. - Qiang Pan; Yitao Wang; Jiayi Chen; Yuekang Guo; Jing Jin 005; Jianjun Zhou 002 (Microelectron. J., 2026)

A 3-5 V to Sub-1 V DLDO-SC-Sigma Converter With Auxiliary Loop for Efficiency Improvement in High-Density Power Delivery. - Yuxiang Li; Jing Jin 005; Yuekang Guo; Jianjun Zhou 002; Junmin Jiang (IEEE J. Solid State Circuits, 2026)

An IR-UWB Transmitter Using Two-Dimensional Differential Pulse Position Modulation. - Dingguo Zhang; Chao Yang; Jianjun Zhou 002; Jing Jin 005 (IEEE Trans. Circuits Syst. II Express Briefs, 2026)

A 3.2-mW Quad-Core CMOS Class-C VCO Achieving 197.1-dBc/Hz Peak FoM at 0.7-V Supply. - Sheng Wang; Chao Yang; Jianjun Zhou 002; Jing Jin 005 (IEEE Trans. Circuits Syst. II Express Briefs, 2026)

A 37-48 GHz Frequency Doubler With >47.8 dBc FRR Utilizing a Staggered Fundamental Suppression Technique. - Yuyang Chen; Chao Yang; Xiaoming Liu 008; Jing Jin 005; Jianjun Zhou 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2026)

A 40-nm CMOS Phase-Tunable Four-Phase Injection-Locked Ring VCO Utilizing Unbalanced Feedforward Topology Achieving -211.1- to -207.3-dBc/Hz FoMA Over Differential/Orthogonal Phase Range of -90.0° to 80.9°/-69.6° to 76.5°. - Huzhi Tang; Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Yi Liu; Zhongyuan Chang; Howard C. Yang; Jianjun Zhou 002 (IEEE J. Solid State Circuits, 2026)