Instruction set extension and hardware acceleration for SVM application toward a vector processor. - Yalong Pang; Jun Han 003; Jianmin Zeng; Yujie Huang; Xiaoyang Zeng (ISOCC, 2017)

A multi-core-based heterogeneous parallel turbo decoder. - Jianmin Zeng; Chubin Wu; Zhang Zhang 004; Xin Cheng 001; Guangjun Xie; Jun Han 003; Xiaoyang Zeng; Zhiyi Yu (IEICE Electron. Express, 2017)

A Qi compatible wireless power receiver with integrated full-wave synchronous rectifier. - Chubin Wu; Zhang Zhang 004; Jianmin Zeng; Xin Cheng 001; Guangjun Xie (Sci. China Inf. Sci., 2018)

A 15 W wireless power receiver with an improved full-wave synchronous rectifier. - Chubin Wu; Guangjun Xie; Zhang Zhang 004; Xin Cheng 001; Tairan Fei; Jianmin Zeng; Xiaoyang Zeng (IEICE Electron. Express, 2018)

Countering power analysis attacks by exploiting characteristics of multicore processors. - Jianwei Yang; Fan Dai; Jielin Wang; Jianmin Zeng; Zhang Zhang 004; Jun Han 003; Xiaoyang Zeng (IEICE Electron. Express, 2018)

A 24-bit sigma-delta ADC with configurable chopping scheme. - Li Li 038; Xu Cheng 002; Zhang Zhang 004; Jianmin Zeng; Xiaoyang Zeng (IEICE Electron. Express, 2019)

High frequency and high efficiency DC-DC converter with sensorless adaptive-sizing technique. - Xin Cheng 001; Wanjing Shao; Yongqiang Zhang 006; Jianmin Zeng; Zhang Zhang 004 (IEICE Electron. Express, 2020)

DM-IMCA: A dual-mode in-memory computing architecture for general purpose processing. - Jianmin Zeng; Zhang Zhang 004; Runhao Chen; Shiyue Liang; Tianlin Cao; Zhiyi Yu; Xin Cheng 001; Guangjun Xie (IEICE Electron. Express, 2020)

A 10T SRAM with Two Read and Write Modes across Row and Column for CAM Operation and Computing In-Memory. - Zhang Zhang 004; Zhihao Chen; Sikai Chen; Guangjun Xie; Jianmin Zeng; Gang Liu (ISCAS, 2024)

Molecular HDD Logic for Encrypted Massive Data Storage. - Bingjie Guo; Xinhui Chen; An Chen; Jinxin Wang; Wuhong Xue; Tao Wang; Zhixin Wu; Xiaolong Zhong; Jianmin Zeng; Jinjin Li; Mao Li; Xiaohong Xu; et al. (CoRR, 2025)