A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. - Wen-Ben Jone; Jiann-Chyi Rau; Shih-Chieh Chang; Yu-Liang Wu (ITC, 1998)

A timing-driven pseudo-exhaustive testing of VLSI circuits. - Shih-Chieh Chang; Jiann-Chyi Rau (ISCAS, 2000)

A compact factored form for a Boolean function. - Jiann-Chyi Rau; Yan-Min Chen; Shih-Chieh Chang (ISCAS, 2000)

A timing-driven pseudoexhaustive testing for VLSI circuits. - Shih-Chieh Chang; Jiann-Chyi Rau (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

A don't-care based image circuit for function verification. - Jiann-Chyi Rau; Yan-Min Chen; Shih-Chieh Chang (ISCAS (5), 2002)

An Efficient Mechanism for Debugging RTL Description. - Jiann-Chyi Rau; Yi-Yuan Chang; Chia-Hung Lin (IWSOC, 2003)

An Enhanced Tree-Structured Scan Chain for Pseudo-Exhaustive Testing of VLSI Circuits. - Jiann-Chyi Rau; Kuo-Chun Kuo (IWSOC, 2003)

An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains. - Jiann-Chyi Rau; Ching-Hsiu Lin; Jun-Yi Chang (Asian Test Symposium, 2004)

Reconfigurable multiple scan-chains for reducing test application time of SOCs. - Jiann-Chyi Rau; Chih-Lung Chien; Jia-Shing Ma (ISCAS (6), 2005)

A novel reseeding mechanism for pseudo-random testing of VLSI circuits. - Jiann-Chyi Rau; Ying-Fu Ho; Po-Han Wu (ISCAS (3), 2005)

Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs. - Jiann-Chyi Rau; Chien-Shiun Chen; Po-Han Wu (APCCAS, 2006)

A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits. - Jiann-Chyi Rau; Po-Han Wu; Chia-Jung Liu (APCCAS, 2006)

A broadcast-based test scheme for reducing test size and application time. - Jiann-Chyi Rau; Jun-Yi Chang; Chien-Shiun Chen (ISCAS, 2006)

An efficient test-data compaction for low power VLSI testing. - Po-Han Wu; Tsung-Tang Chen; Wei-Lin Li; Jiann-Chyi Rau (EIT, 2008)

Test slice difference technique for low power encoding. - Wei-Lin Li; Tsung-Tang Chen; Po-Han Wu; Jiann-Chyi Rau (HLDVT, 2008)

The grid-based two-layer routing algorithm suitable for cell/IP-based circuit design. - Chia-Jung Liu; Yi-Chen Lin; Jiann-Chyi Rau (ICECS, 2008)

New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology. - Tsung-Tang Chen; Wei-Lin Li; Po-Han Wu; Jiann-Chyi Rau (Asian Test Symposium, 2009)

Reducing Switching Activity by Test Slice Difference Technique for Test Volume Compression. - Wei-Lin Li; Po-Han Wu; Jiann-Chyi Rau (ISCAS, 2009)

Low power multi-chains encoding scheme for SoC in low-cost environment. - Po-Han Wu; Jiann-Chyi Rau (ITC, 2009)

Multi-cycle compress technique for high-speed IP in low-cost environment. - Gong-Han Chen; Chu-Chuan Lin; Po-Han Wu; Jiann-Chyi Rau (ISCAS, 2010)

Multi-chains encoding scheme in low-cost ATE. - Gong-Han Chen; Po-Han Wu; Jiann-Chyi Rau (ISCAS, 2010)

The AB-filling methodology for power-aware at-speed scan testing. - Tsung-Tang Chen; Po-Han Wu; Kung-Han Chen; Jiann-Chyi Rau; Shih-Ming Tzeng (ITC, 2010)

Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment. - Jiann-Chyi Rau; Po-Han Wu (IET Comput. Digit. Tech., 2011)

Optimal unknown bit filtering for test response masking. - Ding-ke Weng; Jiann-Chyi Rau; Cheng-Han Lin (ISPACS, 2012)

Compact Test Pattern Selection for Small Delay Defect. - Chia-Yuan Chang; Kuan-Yu Liao; Sheng-Chang Hsu; James Chien-Mo Li; Jiann-Chyi Rau (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

A Scan-Based Lower-Power Testing Architecture for Modern Circuits. - Jiann-Chyi Rau; Jia-Xiang Wang 004 (ISPACS, 2021)

A Hierarchical Tree-Structured Control Digital Low Drop-out Regulator with Status-Dumping Mechanism. - Jiann-Chyi Rau; Wei-Bin Yang; Yu-Lung Lo; Chin-Yuan Shih; Cheng-Kai Lin; Che-Chia Chuang (ISOCC, 2024)