BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework. - Chen Bai; Qi Sun 002; Jianwang Zhai; Yuzhe Ma; Bei Yu 001; Martin D. F. Wong (ICCAD, 2021)

McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs. - Jianwang Zhai; Chen Bai; Binwu Zhu; Yici Cai; Qiang Zhou 001; Bei Yu 001 (ICCAD, 2021)

Placement and Routing Methods Considering Shape Constraints of JTL for RSFQ Circuits. - Jianwang Zhai; Yici Cai; Qiang Zhou 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning. - Jianwang Zhai; Yici Cai; Bei Yu 001 (ASP-DAC, 2023)

McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework. - Jianwang Zhai; Chen Bai; Binwu Zhu; Yici Cai; Qiang Zhou 001; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Microarchitecture Design Space Exploration via Pareto-Driven Active Learning. - Jianwang Zhai; Yici Cai (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning. - Chen Bai; Jianwang Zhai; Yuzhe Ma; Bei Yu 001; Martin D. F. Wong (AAAI, 2024)

Fast Estimation for Electromigration Nucleation Time Based on Random Activation Energy Model. - Jingyu Jia; Jianwang Zhai; Kang Zhao (DATE, 2024)

PGAU: Static IR Drop Analysis for Power Grid using Attention U-Net Architecture and Label Distribution Smoothing. - Feng Guo; Jiawei Liu 006; Jianwang Zhai; Jingyu Jia; Kang Zhao; Chuan Shi 001 (ACM Great Lakes Symposium on VLSI, 2024)

PolarGate: Breaking the Functionality Representation Bottleneck of And-Inverter Graph Neural Network. - Jiawei Liu 006; Jianwang Zhai; Mingyu Zhao; Zhe Lin 001; Bei Yu 001; Chuan Shi 001 (ICCAD, 2024)

Effective Resource Model and Cost Scheme for Maze Routing in 3D Global Routing. - Zirui Li; Jianwang Zhai; Zixuan Li; Zhongdong Qi; Kang Zhao (ISCAS, 2024)

The Survey of Chiplet-based Integrated Architecture: An EDA perspective. - Shixin Chen; Hengyuan Zhang; Zichao Ling; Jianwang Zhai; Bei Yu 001 (CoRR, 2024)

BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration. - Chen Bai; Qi Sun 002; Jianwang Zhai; Yuzhe Ma; Bei Yu 001; Martin D. F. Wong (ACM Trans. Design Autom. Electr. Syst., 2024)

The Survey of 2.5D Integrated Architecture: An EDA perspective. - Shixin Chen; Hengyuan Zhang; Zichao Ling; Jianwang Zhai; Bei Yu 001 (ASP-DAC, 2025)

PIRLLS: Pretraining with Imitation and RL Finetuning for Logic Synthesis. - Guande Dong; Jianwang Zhai; Hongtao Cheng; Xiao Yang; Chuan Shi 001; Kang Zhao (ASP-DAC, 2025)

FTAFP: A Feedthrough-Aware Floorplanner for Hierarchical Design of Large-Scale SoCs. - Zirui Li; Kanglin Tian; Jianwang Zhai; Zixuan Li; Shixiong Kai; Siyuan Xu; Bei Yu 001; Kang Zhao (ASP-DAC, 2025)

IR-Fusion: A Fusion Framework for Static IR Drop Analysis Combining Numerical Solution and Machine Learning. - Feng Guo; Jianwang Zhai; Jingyu Jia; Jiawei Liu 006; Kang Zhao; Bei Yu 001; Chuan Shi 001 (DATE, 2025)

WideGate: Beyond Directed Acyclic Graph Learning in Subcircuit Boundary Prediction. - Jiawei Liu 006; Zhiyan Liu; Xun He; Jianwang Zhai; Zhengyuan Shi; Qiang Xu 001; Bei Yu 001; Chuan Shi 001 (DATE, 2025)

AuxiliarySRAM: Exploring Elastic On-Chip Memory in 2.5D Chiplet Systems Design. - Zichao Ling; Lin Li; Yi Huang; Yixin Xuan; Jianwang Zhai; Kang Zhao (ACM Great Lakes Symposium on VLSI, 2025)

MILS: Modality Interaction Driven Learning for Logic Synthesis. - Mingyu Zhao; Jiawei Liu 006; Jianwang Zhai; Chuan Shi 001 (ACM Great Lakes Symposium on VLSI, 2025)

HieRFP: A Hierarchical Recognition and Floorplanning Framework for Reusable Modules. - Zixuan Li; Kanglin Tian; Jianwang Zhai; Zirui Li; Kang Zhao (ISCAS, 2025)

Transferable Parasitic Estimation via Graph Contrastive Learning and Label Rebalancing in AMS Circuits. - Shan Shen; Shenglu Hua; Jiajun Zou; Jiawei Liu 006; Jianwang Zhai; Chuan Shi 001; Wenjian Yu (CoRR, 2025)