A novel SEU tolerant memory cell for space applications. - Dianpeng Lin; Yiran Xu; Xiaoyun Li; Xin Xie; Jianwei Jiang 001; Jiangchuan Ren; Huilong Zhu; Zhengxuan Zhang; Shichang Zou (IEICE Electron. Express, 2018)

A novel self-recoverable and triple nodes upset resilience DICE latch. - Dianpeng Lin; Yiran Xu; Xiaoyun Li; Xin Xie; Jianwei Jiang 001; Jiangchuan Ren; Huilong Zhu; Zhengxuan Zhang; Shichang Zou (IEICE Electron. Express, 2018)

A novel highly reliable and low-power radiation hardened SRAM bit-cell design. - Dianpeng Lin; Yiran Xu; Xiaonian Liu; Wenyi Zhu; Lihua Dai; Mengying Zhang; Xiaoyun Li; Xin Xie; Jianwei Jiang 001; Huilong Zhu; Zhengxuan Zhang; Shichang Zou (IEICE Electron. Express, 2018)

Soft-Error-Tolerant Ultralow-Leakage 12T SRAM Bitcell Design. - Jianwei Jiang 001; Dianpeng Lin; Jun Xiao; Shichang Zou (ICICDT, 2019)

A charge pump system with new regulation and clocking scheme. - Wenyi Zhu; Jianwei Jiang 001; Dianpeng Lin; Jun Xiao; Guangjun Yang; Xiaoyun Li; Shichang Zou (IEICE Electron. Express, 2019)

Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications. - Jianwei Jiang 001; Yiran Xu; Wenyi Zhu; Jun Xiao; Shichang Zou (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Wide-Range-Supply-Voltage Sense Amplifier Circuit for Embedded Flash Memory. - Wenyi Zhu; Jianwei Jiang 001; Haineng Zhang; Yiran Xu; Jun Xiao; Guangjun Yang; Shichang Zou (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch Design. - Zhongyang Liu; Haineng Zhang; Jianwei Jiang 001; Yanjie Jia; Yuqiao Xie; Shichang Zou; Zhengxuan Zhang (IEEE Trans. Very Large Scale Integr. Syst., 2022)