IP-Centric Methodology and Specification Language. - Daniel Gajski; Rainer Dömer; Jianwen Zhu (DIPES, 1998)

Specification and Design of Embedded Systems. - Rainer Dömer; Daniel D. Gajski; Jianwen Zhu (Informationstechnik Tech. Inform., 1998)

A unified formal model of ISA and FSMD. - Jianwen Zhu; Daniel Gajski (CODES, 1999)

Soft Scheduling in High Level Synthesis. - Jianwen Zhu; Daniel Gajski (DAC, 1999)

OpenJ: An Extensible System Level Design Language. - Jianwen Zhu; Daniel Gajski (DATE, 1999)

Compiling SpecC for simulation. - Jianwen Zhu; Daniel Gajski (ASP-DAC, 2001)

MetaRTL: raising the abstraction level of RTL design. - Jianwen Zhu (DATE, 2001)

Static memory allocation by pointer analysis and coloring. - Jianwen Zhu (DATE, 2001)

Color Permutation: An Iterative Algorithm for Memory Packing. - Jianwen Zhu; Edward S. Rogers Sr. (ICCAD, 2001)

Retargetable binary utilities. - Maghsoud Abbaspour; Jianwen Zhu (DAC, 2002)

Hardware Implementation of a Memory Allocator. - Khushwinder Jasrotia; Jianwen Zhu (DSD, 2002)

Symbolic pointer analysis. - Jianwen Zhu (ICCAD, 2002)

An ultra-fast instruction set simulator. - Jianwen Zhu; Daniel D. Gajski (IEEE Trans. Very Large Scale Integr. Syst., 2002)

A retargetable micro-architecture simulator. - Wai Sum Mong; Jianwen Zhu (DAC, 2003)

Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching. - Zhong Wang; Jianwen Zhu (DATE, 2003)

Specification of Non-Functional Intellectual Property Components. - Jianwen Zhu; Wai Sum Mong (DATE, 2003)

Performance Efficiency of Context-Flow System-on-Chip Platform. - Rami Beidas; Jianwen Zhu (ICCAD, 2003)

Automatic process migration of datapath hard IP libraries. - Fang Fang; Jianwen Zhu (ASP-DAC, 2004)

Piecewise quadratic waveform matching with successive chord iteration. - Zhong Wang; Jianwen Zhu (ASP-DAC, 2004)

An analytical approach for dynamic range estimation. - Bin Wu; Jianwen Zhu; Farid N. Najm (DAC, 2004)

A queuing-theoretic performance model for context-flow system-on-chip platforms. - Rami Beidas; Jianwen Zhu (ESTIMedia, 2004)

DynamoSim: a trace-based dynamically compiled instruction set simulator. - Massimo Poncino; Jianwen Zhu (ICCAD, 2004)

Dynamic range estimation for nonlinear systems. - Bin Wu; Jianwen Zhu; Farid N. Najm (ICCAD, 2004)

Calligrapher: A New Layout Migration Engine Based on Geometric Closeness. - Fang Fang; Jianwen Zhu (ISQED, 2004)

Stacked FSMD: A Power Efficient Micro-Architecture for High Level Synthesis. - Khushwinder Jasrotia; Jianwen Zhu (ISQED, 2004)

Symbolic pointer analysis revisited. - Jianwen Zhu; Silvian Calman (PLDI, 2004)

Scalable interprocedural register allocation for high level synthesis. - Rami Beidas; Jianwen Zhu (ASP-DAC, 2005)

BDD-based two variable sharing extraction. - Dennis Wu; Jianwen Zhu (ASP-DAC, 2005)

A non-parametric approach for dynamic range estimation of nonlinear systems. - Bin Wu; Jianwen Zhu; Farid N. Najm (DAC, 2005)

Towards scalable flow and context sensitive pointer analysis. - Jianwen Zhu (DAC, 2005)

Two-Dimensional Layout Migration by Soft Constraint Satisfaction. - Qianying Tang; Jianwen Zhu (ISQED, 2005)

Context sensitive symbolic pointer analysis. - Jianwen Zhu; Silvian Calman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Calligrapher: a new layout-migration engine for hard intellectual property libraries. - Jianwen Zhu; Fang Fang; Qianying Tang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Dynamic-range estimation. - Bin Wu; Jianwen Zhu; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

BddCut: Towards Scalable Symbolic Cut Enumeration. - Andrew C. Ling; Jianwen Zhu; Stephen Dean Brown (ASP-DAC, 2007)

Delay driven AIG restructuring using slack budget management. - Andrew C. Ling; Jianwen Zhu; Stephen Dean Brown (ACM Great Lakes Symposium on VLSI, 2008)

Scalable Synthesis and Clustering Techniques Using Decision Diagrams. - Andrew C. Ling; Jianwen Zhu; Stephen Dean Brown (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Towards automated ECOs in FPGAs. - Andrew C. Ling; Stephen Dean Brown; Jianwen Zhu; Sean Safarpour (FPGA, 2009)

VariPipe: Low-overhead variable-clock synchronous pipelines. - Navid Toosizadeh; Safwat G. Zaky; Jianwen Zhu (ICCD, 2009)

Increasing the Scope and Resolution of Interprocedural Static Single Assignment. - Silvian Calman; Jianwen Zhu (SAS, 2009)

Towards scalable placement for FPGAs. - Huimin Bian; Andrew C. Ling; Alexander Choong; Jianwen Zhu (FPGA, 2010)

A 1 cycle-per-byte XML parsing accelerator. - Zefu Dai; Nick Ni; Jianwen Zhu (FPGA, 2010)

Parallelizing Simulated Annealing-Based Placement Using GPGPU. - Alexander Choong; Rami Beidas; Jianwen Zhu (FPL, 2010)

Credit Borrow and Repay: Sharing DRAM with minimum latency and bandwidth guarantees. - Zefu Dai; Mark Jarvin; Jianwen Zhu (ICCAD, 2010)

Using variable clocking to reduce leakage in synchronous circuits. - Navid Toosizadeh; Safwat G. Zaky; Jianwen Zhu (ICCD, 2010)

Interprocedural induction variable analysis based on interprocedural SSA form IR. - Silvian Calman; Jianwen Zhu (PASTE, 2010)

On virtual prototyping of embedded system-on-chips. - Yi Ni; Wai Sum Mong; Jianwen Zhu (ASICON, 2011)

Register pressure aware scheduling for high level synthesis. - Rami Beidas; Wai Sum Mong; Jianwen Zhu (ASP-DAC, 2011)

A bursty multi-port memory controller with quality-of-service guarantees. - Zefu Dai; Jianwen Zhu (CODES+ISSS, 2011)

Regular fabric for regular FPGA (abstract only). - Xun Chen; Jianwen Zhu (FPGA, 2011)

Timing-Driven Routing of High Fanout Nets. - Xun Chen; Jianwen Zhu; Minxuan Zhang (FPL, 2011)

Toward Automated ECOs in FPGAs. - Andrew C. Ling; Stephen Dean Brown; Sean Safarpour; Jianwen Zhu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Saturating the transceiver bandwidth: switch fabric design on FPGAs. - Zefu Dai; Jianwen Zhu (FPGA, 2012)

Analytical modeling of garbage collection algorithms in hotness-aware flash-based solid state drives. - Yue Yang; Jianwen Zhu (MSST, 2014)

Algebraic modeling of write amplification in hotness-aware SSD. - Yue Yang; Jianwen Zhu (SYSTOR, 2015)

A Sufficient Condition for Deadlock-Free Adaptive Routing in Mesh Networks. - Canwen Xiao; Yue Yang; Jianwen Zhu (IEEE Comput. Archit. Lett., 2015)

Write Amplification with Write Skew. - Yue Yang; Jianwen Zhu (MASCOTS, 2016)

Write Skew and Zipf Distribution: Evidence and Implications. - Yue Yang; Jianwen Zhu (ACM Trans. Storage, 2016)

A Case for Common-Case: On FPGA Acceleration of Erasure Coding. - Reza Nakhjavani; Jianwen Zhu (FCCM, 2017)

A fast Bayesian algorithmic enhancement for real time bit error ratio test (BERT). - Shu-Yi Jack Wong; Jianwen Zhu (GlobalSIP, 2017)

Rotary Register File: A Micro-Architectural Primitive on FPGA. - Reza Nakhjavani; Jianwen Zhu (FCCM, 2020)

Multi-constrained intelligent gliding guidance via optimal control and DQN. - Jianwen Zhu; Hao Zhang; Sibo Zhao; Weimin Bao (Sci. China Inf. Sci., 2023)

A unified intelligent control strategy synthesizing multi-constrained guidance and avoidance penetration. - Sibo Zhao; Jianwen Zhu; Weimin Bao; Xiaoping Li (Sci. China Inf. Sci., 2024)

The Unconditional Consensus Control through Leadership for the Delayed Hegselmann-Krause Model. - Linglong Du; Jianwen Zhu; Feng Xie (SIAM J. Control. Optim., 2024)